NEETS, MODULE 09--INTRODUCTION TO WAVE-GENERATION AND WAVE-SHAPING CIRCUITS

NEETS MODULE 9-Wave Generation and Wave Shaping UNCLASSIFIED

3-1 UNCLASSIFIED 3 WA VEFORMS AND WA VE GENERATORS LEARNING OBJECTIVES After you finish this chapter, you should be able to do the following: 1. Explain the operation of a stable, monostable, and bistable multivibrators. 2. Explain the operation of a blocking oscillator. 3. Explain the operation of a sawtooth generator. 4. Explain the operation of a trapezoidal wave generator. 5. Explain how the jump voltage is produced in a trapezoidal wave generator.

3.1 WAVEFORMS This chapter will present methods of generating waveforms. Before you begin to study how waveforms are generated, you need to know the basic characteristics of waveforms. This section will discuss basic periodic waveforms.

3.1.1 Periodic Waveforms A waveform which undergoes a pattern of changes, returns to its original pattern, and repeats the same pattern of changes is called a PERIODIC waveform. Periodic waveforms are nonsinusoidal except for the sine wave. Periodic waveforms which will be discussed are the sine wave, square wave, rectangular wave, sawtooth wave, trapezoidal wave, and trigger pulses.

3.1.1.1 Sine Wave Each completed pattern of a periodic waveform is called a CYCLE, as shown by the SINE WAVE in figure 3-1, view (A). Sine waves were presented in NEETS, Module 2, Alternating Current and Transformers, Chapter 1.

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3.1.1.2 Square Wave A SQUARE WAVE is shown in figure 3-1, view (B). As shown, it has two alternations of equal duration and a square presentation for each complete cycle. Figure 3-2 shows a breakdown of the square wave and is the figure you should view throughout the square wave discussion. The amplitude is measured vertically. The time for a complete cycle is measured between corresponding points on the wave (T0 to T2, or T1 to T3).

Figure 3-1 Periodic waveforms

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One alternation is called a PULSE. The time for one complete cycle is called the PULSE REPETITION TIME (prt). The number of times in 1 second that the cycle repeats itself is called the PULSE-REPETITION FREQUENCY (prf) or PULSE-REPETITION RATE (prr). If each alternation in figure 3-2 is 200 microseconds (μs), the prt will be 400 microseconds, and the prf will be 2,500 hertz. The following examples are provided to illustrate the mathematical relationship between prf and prt:

Figure 3-2 Square wave

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3-4 UNCLASSIFIED You should readily see that prt is just the inverse of prf. Therefore: Given:

The length of the pulse measured in time (T0 to T1) is referred to as the PULSE WIDTH (pw). The left side of the pulse is called the LEADING EDGE and the right side is called the TRAILING EDGE.

Time is required for a voltage or current to change in amplitude. The interval of time needed for the voltage to go from 0 to 100 percent (or from 100 to 0 percent) of its maximum value is called the TRANSIENT INTERVAL. The two types of transient intervals are RISE TIME and FALL TIME. Rise time is more accurately defined as the time required for the voltage to build up from 10 percent to 90 percent of the maximum amplitude point. Fall time is the time required for the voltage to drop from 90 percent to 10 percent of the maximum amplitude point.

In this text you will be presented with information in which waveforms appear to have instantaneous rise and fall times. This is done to simplify the presentation of the material. In reality these waveforms do have rise and fall times (transient intervals).

NEETS MODULE 9-Wave Generation and Wave Shaping UNCLASSIFIED

3-5 UNCLASSIFIED 3.1.1.3 Rectangular Wave A rectangular wave is similar to the square wave. The difference is that in the rectangular waveform, the two alternations of the waveform are of unequal time duration. Figure 3-1, view (C), shows that the negative alternation (pulse) is shorter (in time) than the positive alternation. The negative alternation could be represented as the longer of the two alternations. Either way, the appearance is that of a rectangle.

3.1.1.4 Sawtooth Wave The SAWTOOTH waveform is shown in figure 3-1, view (D). A sawtooth wave resembles the teeth of a saw blade. There is a rapid vertical rise of voltage from T0 to T1, which is linear (straight). At T1 this voltage abruptly falls (essentially no time used) to its previous static value. The voltage remains at this value until T2 when it again has a linear rise. You can see this action in an oscilloscope where there are two voltage input locations, vertical and horizontal. If you apply a linear voltage to the vertical input, the electron beam will be forced to move in a vertical direction on the crt. A linear voltage applied to the horizontal input will cause the electron beam to move horizontally across the crt. The application of two linear voltages, one to the vertical input and one to the horizontal input at the same time, will cause the beam to move in both a vertical and horizontal (diagonal) direction at the same time. This then is how a sawtooth wave is made to appear on an oscilloscope. You should refer to NEETS, Module 6, Electronic Emission, Tubes, and Power Supplies, Chapter 2, for a review of oscilloscopes.

3.1.1.5 Trapezoidal Wave A TRAPEZOIDAL wave looks like a sawtooth wave on top of a square or rectangular wave, as shown in figure 3-1, view (E). The leading edge of a trapezoidal wave is called the JUMP voltage. The next portion of the wave is the linear rise or SLOPE. The trailing edge is called the FALL or DECAY. A trapezoidal wave is used to furnish deflection current in the electromagnetic cathode ray tube and is found in television and radar display systems. Electromagnetic cathode ray tubes use coils for the deflection system, and a linear rise in current is required for an accurate horizontal display. The square or rectangular wave portion provides the jump voltage for a linear rise in current through the resistance of the coil. This will be explained further in a discussion of the trapezoidal sweep generator.

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3-6 UNCLASSIFIED 3.1.1.6 Triggers A trigger is a very narrow pulse, as shown in figure 3-1, view (F). Trigger pulses are normally used to turn other circuits on or off.

3.2 WAVEFORM GENERATOR Nonsinusoidal oscillators generate complex waveforms such as those just discussed. Because the outputs of these oscillators are generally characterized by a sudden change, or relaxation, these oscillators are often called RELAXATION OSCILLATORS. The pulse repetition rate of these oscillators is usually governed by the charge and discharge timing of a capacitor in series with a resistor. However, some oscillators contain inductors that, along with circuit resistance, affect the output frequency. These RC and LC networks within oscillator circuits are used for frequency determination. Within this category of relaxation oscillators are MULTIVIBRATORS, BLOCKING OSCILLATORS, and SAWTOOTH- and TRAPEZOIDAL-WAVE GENERATORS.

Many electronic circuits are not in an "on" condition all of the time. In computers, for example, waveforms must be turned on and off for specific lengths of time. The time intervals vary from tenths of microseconds to several thousand microseconds. Square and rectangular waveforms are normally used to turn such circuits on and off because the sharp leading and trailing edges make them ideal for timing purposes.

3.2.1 Multivibrators The type of circuit most often used to generate square or rectangular waves is the multivibrator. A multivibrator, as shown in figure 3-3, is basically two amplifier circuits arranged with regenerative feedback. One of the amplifiers is conducting while the other is cut off.

Figure 3-3 Astable Multivibrator

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3-7 UNCLASSIFIED When an input signal to one amplifier is large enough, the transistor can be driven into cutoff, and its collector voltage will be almost VCC. However, when the transistor is driven into saturation, its collector voltage will be about 0 volts. A circuit that is designed to go quickly from cutoff to saturation will produce a square or rectangular wave at its output. This principle is used in multivibrators.

Multivibrators are classified according to the number of steady (stable) states of the circuit. A steady state exists when circuit operation is essentially constant; that is, one transistor remains in conduction and the other remains cut off until an external signal is applied. The three types of multivibrators are the ASTABLE, MONOSTABLE, and BISTABLE.

The astable circuit has no stable state. With no external signal applied, the transistors alternately switch from cutoff to saturation at a frequency determined by the RC time constants of the coupling circuits.

The monostable circuit has one stable state; one transistor conducts while the other is cut off. A signal must be applied to change this condition. After a period of time, determined by the internal RC components, the circuit will return to its original condition where it remains until the next signal arrives.

The bistable multivibrator has two stable states. It remains in one of the stable states until a trigger is applied. It then FLIPS to the other stable condition and remains there until another trigger is applied. The multivibrator then changes back (FLOPS) to its first stable state.

Q1. What type circuit is used to produce square or rectangular waves? Q2. What type of multivibrator does not have a stable state? Q3. What type of multivibrator has one stable state? Q4. What type of multivibrator has two stable states?

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3-8 UNCLASSIFIED 3.2.1.1 Astable Multivibrator An astable multivibrator is also known as a FREE-RUNNING MULTIVIBRATOR. It is called free running because it alternates between two different output voltage levels during the time it is on. The output remains at each voltage level for a definite period of time. If you looked at this output on an oscilloscope, you would see continuous square or rectangular waveforms. The astable multivibrator has two outputs, but NO inputs.

Let's look at the multivibrator in figure 3-3 again. This is an astable multivibrator. The astable multivibrator is said to oscillate. To understand why the astable multivibrator oscillates, assume that transistor Q1 saturates and transistor Q2 cuts off when the circuit is energized. This situation is shown in figure 3-4. We assume Q1 saturates and Q2 is in cutoff because the circuit is symmetrical; that is, R1 = R4, R2 = R3, C1 = C2, and Q1 = Q2. It is impossible to tell which transistor will actually conduct when the circuit is energized. For this reason, either of the transistors may be assumed to conduct for circuit analysis purposes.

Figure 3-4 Astable multivibrator (Q1 saturated)

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3-9 UNCLASSIFIED Essentially, all the current in the circuit flows through Q1; Q1 offers almost no resistance to current flow. Notice that capacitor C1 is charging. Since Q1 offers almost no resistance in its saturated state, the rate of charge of C1 depends only on the time constant of R2 and C1 (recall that TC = RC). Notice that the right-hand side of capacitor C1 is connected to the base of transistor Q2, which is now at cutoff.

Let's analyze what is happening. The right-hand side of capacitor C1 is becoming increasingly negative. If the base of Q2 becomes sufficiently negative, Q2 will conduct. After a certain period of time, the base of Q2 will become sufficiently negative to cause Q2 to change states from cutoff to conduction. The time necessary for Q2 to become saturated is determined by the time constant R2C1.

The next state is shown in figure 3-5. The negative voltage accumulated on the right side on capacitor C1 has caused Q2 to conduct. Now the following sequence of events takes place almost instantaneously. Q2 starts conducting and quickly saturates, and the voltage at output 2 changes from approximately −V CC to approximately 0 volts. This change in voltage is coupled through C2 to the base of Q1, forcing Q1 to cutoff. Now Q1 is in cutoff and Q2 is in saturation. This is the circuit situation shown in figure 3-6.

Figure 3-5 Astable multivibrator

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Notice that figure 3-6 is the mirror image of figure 3-4. In figure 3-6 the left side of capacitor C2 becomes more negative at a rate determined by the time constant R3C2. As the left side of C2 becomes more negative, the base of Q1 also becomes more negative. When the base of Q1 becomes negative enough to allow Q1 to conduct, Q1 will again go into saturation. The resulting change in voltage at output 1 will cause Q2 to return to the cutoff state.

Look at the output waveform from transistor Q2, as shown in figure 3-7. The output voltage (from either output of the multivibrator) alternates from approximately 0 volts to approximately −V CC, remaining in each state for a definite period of time. The time may range from a microsecond to as much as a second or two. In some applications, the time period of higher voltage (−VCC) and the time period of lower voltage (0 volts) will be equal. Other applications require differing higher- and lower-voltage times. For example, timing and gating circuits often have different pulse widths as shown in figure 3-8.

Figure 3-6 Astable multivibrator. (Q2 saturated)

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FREQUENCY STABILITY.—Some astable multivibrators must have a high degree of frequency stability. One way to obtain a high degree of frequency stability is to apply triggers. Figure 3-9, view (A), shows the diagram of a triggered, astable multivibrator. At time T0, a negative input trigger to the base of Q1 (through C1) causes Q1 to go into saturation, which drives Q2 to cutoff. The circuit will remain in this condition as long as the base voltage of Q2 is positive. The length of time the base of Q2 will remain positive is determined by C3, R3, and R6. Observe the parallel paths for C3 to discharge.

Figure 3-7 Square wave output from Q2 Figure 3-8 Rectangular waves

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View (B) of figure 3-9 shows the waveforms associated with the circuit. At time T1, Q2 comes out of cutoff and goes into saturation. Also, Q1 is caused to come out of saturation and is cut off. The base voltage waveform of Q1 shows a positive potential that is holding Q1 at cutoff. This voltage would normally hold Q1 at cutoff until a point between T2 and T3. However, at time T2 another trigger is applied to the base of Q1, causing it to begin conducting. Q1 goes into saturation and Q2 is caused to cut off. This action repeats each time a trigger (T2, T4, T6) is applied.

Figure 3-9A Triggered astable multivibrator and output Figure 3-9B.— Triggered astable multivibrator and output

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3-13 UNCLASSIFIED The prt of the input triggers must be shorter than the natural free-running prt of the astable multivibrator, or the trigger prf must be slightly higher than the free-running prf of the circuit. This is to make certain the triggers control the prt of the output.

3.2.1.2 Monostable Multivibrator The monostable multivibrator (sometimes called a ONE-SHOT MULTIVIBRATOR) is a square- or rectangular-wave generator with just one stable condition. With no input signal (quiescent condition) one amplifier conducts and the other is in cutoff. The monostable multivibrator is basically used for pulse stretching. It is used in computer logic systems and communication navigation equipment.

The operation of the monostable multivibrator is relatively simple. The input is triggered with a pulse of voltage. The output changes from one voltage level to a different voltage level. The output remains at this new voltage level for a definite period of time. Then the circuit automatically reverts to its original condition and remains that way until another trigger pulse is applied to the input. The monostable multivibrator actually takes this series of input triggers and converts them to uniform square pulses, as shown in figure 3- 10. All of the square output pulses are of the same amplitude and time duration.

The schematic for a monostable multivibrator is shown in figure 3-11. Like the astable multivibrator, one transistor conducts and the other cuts off when the circuit is energized.

Figure 3-10 Monostable multivibrator block diagram

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Recall that when the astable multivibrator was first energized, it was impossible to predict which transistor would initially go to cutoff because of circuit symmetry. The one-shot circuit is not symmetrical like the astable multivibrator. Positive voltage V BB is applied through R5 to the base of Q1. This positive voltage causes Q1 to cut off. Transistor Q2 saturates because of the negative voltage applied from −VCC to its base through R2. Therefore, Q1 is cut off and Q2 is saturated before a trigger pulse is applied, as shown in figure 3-12. The circuit is shown in its stable state.

Figure 3-11 Monostable multivibrator schematic Figure 3-12 Monostable multivibrator (stable state)

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3-15 UNCLASSIFIED Let's take a more detailed look at the circuit conditions in this stable state (refer to figure 3-12). As stated above, Q1 is cut off, so no current flows through R1, and the collector of Q1 is at −VCC. Q2 is saturated and has practically no voltage drop across it, so its collector is essentially at 0 volts. R5 and R3 form a voltage divider from VBB to the ground potential at the collector of Q2. The tie point between these two resistors will be positive. Thus, the base of Q1 is held positive, ensuring that Q1 remains cutoff. Q2 will remain saturated because the base of Q2 is very slightly negative as a result of the voltage drop across R2. If the collector of Q1 is near −V CC and the base of Q2 is near ground, C1 must be charged to nearly VCC volts with the polarity shown.

Now that all the components and voltages have been described for the stable state, let us see how the circuit operates (see figure 3-13). Assume that a negative pulse is applied at the input terminal. C2 couples this voltage change to the base of Q1 and starts Q1 conducting. Q1 quickly saturates, and its collector voltage immediately rises to ground potential. This sharp voltage increase is coupled through C1 to the base of Q2, causing Q2 to cut off; the collector voltage of Q2 immediately drops to VCC. The voltage divider formed by R5 and R3 then holds the base of Q1 negative, and Q1 is locked in saturation.

Figure 3-13 Monostable multivibrator (triggered)

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3-16 UNCLASSIFIED The one-shot multivibrator has now been turned on by applying a pulse at the input. It will turn itself off after a period of time. To see how it does this, look at figure 3-13 again. Q1 is held in saturation by the negative voltage applied through R3 to its base, so the circuit cannot be turned off here. Notice that the base of Q2 is connected to C1. The positive charge on C1 keeps Q2 cutoff. Remember that a positive voltage change (essentially a pulse) was coupled from the collector of Q1 when it began conducting to the base of Q2, placing Q2 in cutoff. When the collector of Q1 switches from -VCC volts to 0 volts, the charge on C1 acts like a battery with its negative terminal on the collector of Q1, and its positive terminal connected to the base of Q2. This voltage is what cuts off Q2. C1 will now begin to discharge through Q1 to ground, back through −V CC, through R2 to the other side of C1. The time required for C1 to discharge depends on the RC time constant of C1 and R2. Figure 3-14 is a timing diagram that shows the negative input pulse and the resultant waveforms that you would expect to see for this circuit description.

The only part of the operation not described so far is the short C1 charge time that occurs right after Q1 and Q2 return to their stable states. This is simply the time required for C1 to gain electrons on its left side. This charge time is determined by the R1C1 time constant.

Figure 3-14 Waveforms of a monostable multivibrator (triggered)

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3-17 UNCLASSIFIED Another version of the monostable multivibrator is shown in figure 3-15. View (A) is the circuit and view (B) shows the associated waveforms. In its stable condition (T0), Q1 is cut off and Q2 is conducting. The input trigger (positive pulse at T1) is applied to the collector of Q1 and coupled by C1 to the base of Q2 causing Q2 to be cut off. The collector voltage of Q2 then goes −VCC. The more negative voltage at the collector of Q2 forward biases Q1 through R4. With the forward bias, Q1 conducts, and the collector voltage of Q1 goes to about 0 volts. C1 now discharges and keeps Q2 cut off. Q2 remains cut off until C1 discharges enough to allow Q2 to conduct again (T2). When Q2 conducts again, its collector voltage goes toward 0 volts and Q1 is cut off. The circuit returns to its quiescent state and has completed a cycle. The circuit remains in this stable state until the next trigger arrives (T3).

Figure 3-15A Monostable multivibrator and waveshapes. Schematic

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Note that R3 is variable to allow adjustment of the gate width. Increasing R3 increases the discharge time for C1 which increases the cutoff time for Q2. Increasing the value of R3 widens the gate. To decrease the gate width, decrease the value of R3. Figure 3-16 shows the relationships between the trigger and the output signal. View (A) of the figure shows the input trigger; views (B) and (C) show the different gate widths made available by R3. Although the durations of the gates are different, the duration of the complete cycle remains the same as the pulse repetition time of the triggers. View (D) of the figure illustrates that the trailing edge of the positive alternation is variable.

Figure 3-15B.— Monostable multivibrator and waveshapes. Waveshapes Figure 3-16 Monostable multivibrator waveforms with a variable gate

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3-19 UNCLASSIFIED The reason the monostable multivibrator is also called a one-shot multivibrator can easily be seen. For every trigger pulse applied to the multivibrator, a complete cycle, or a positive and negative alternation of the output, is completed.

Q5. In an astable multivibrator, which components determine the pulse repetition frequency? Q6. What is another name for the monostable multivibrator? 3.2.1.3 Bistable Multivibrator As the name implies, the bistable multivibrator has two stable states. If a trigger of the correct polarity and amplitude is applied to the circuit, it will change states and remain there until triggered again. The trigger need not have a fixed prf; in fact, triggers from different sources, occurring at different times, can be used to switch this circuit.

The bistable multivibrator circuit and the associated waveforms are shown in figure 3-17, views (A) and (B), respectively. In this circuit, R1 and R7 are the collector load resistors. Voltage dividers R1, R2, and R5 provide forward bias for Q2; R7, R6, and R3 provide forward bias for Q1. These resistors also couple the collector signal from one transistor to the base of the other. Observe that this is direct coupling of feedback. This type of coupling is required because the circuit depends on input triggers for operation, not on RC time constants inside the circuit. Both transistors use common emitter resistor R4 which provides emitter coupling. C1 and C2 couple the input triggers to the transistor bases.

Figure 3-17A Bistable multivibrator and waveforms

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Notice that the circuit is symmetrical; that is, each transistor amplifier has the same component values. When power is first applied, the voltage divider networks place a negative voltage at the bases of Q1 and Q2. Both transistors have forward bias and both conduct.

Due to some slight difference between the two circuits, one transistor will conduct more than the other. Assume that Q1 conducts more than Q2. The increased conduction of Q1 causes the collector voltage of Q1 to be less negative (more voltage drop across R1). This decreases the forward bias of Q2 and decreases the conduction of Q2. When Q2 conducts less, its collector voltage becomes more negative. The negative-going change at the collector of Q2 is coupled to the base of Q1 and causes Q1 to conduct even more heavily. This regenerative action continues until Q2 is cut off and Q1 is saturated. The circuit is in a stable state and will remain there until a trigger is applied to change the state.

At T1, a negative trigger is applied to both bases through C1 and C2. The trigger does not affect Q1 since it is already conducting. The trigger overcomes cutoff bias on Q2 and causes it to conduct. As Q2 goes into conduction, its collector voltage becomes positive. The positive-going change at the Q2 collector causes a reverse bias on the base of Q1. As the conduction of Q1 decreases to the cutoff point, the collector voltage becomes negative. This switching action causes a very rapid change of state with Q2 now conducting and Q1 cut off.

Figure 3-17B.— Bistable multivibrator and waveforms

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3-21 UNCLASSIFIED At T2, a negative trigger is again applied to both bases. This time, Q1 is brought into conduction and the regenerative switching action cuts off Q2. The bistable multivibrator will continue to change states as long as triggers are applied. Notice that two input triggers are required to produce one gate; one to turn it on and the other to turn it off. The input trigger frequency is twice the output frequency.

The bistable multivibrator that most technicians know is commonly known by other names: the ECCLES-JORDAN circuit and, more commonly, the FLIP-FLOP circuit (figure 3-18). The flip-flop is a bistable multivibrator, "bi" meaning two; that is, the flip- flop has two stable states. The flip-flop (f/f) can rapidly flip from one state to the other and then flop back to its original state. If a voltmeter were connected to the output of a flip-flop, it would measure either a small positive or negative voltage, or a particularly low voltage (essentially 0 volts). No matter which voltage is measured, the flip-flop would be stable. Remember, stable means that the flip-flop will remain in a particular state indefinitely. It will not change states unless the proper type of trigger pulse is applied.

Figure 3-18 Basic flip-flop

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3-22 UNCLASSIFIED Flip-flops are used in switching-circuit applications (computer logic operations) as counters, shift registers, clock pulse generators, and in memory circuits. They are also used for relay-control functions and for a variety of similar applications in radar and communications systems.

Notice that the basic flip-flop, illustrated in figure 3-18, has two inputs and two outputs. The inputs are coupled to the bases of the transistors and the outputs are coupled from the collectors of the transistors. Think of the flip-flop as two common-emitter amplifier circuits, where the output of one amplifier is connected to the input of the other amplifier, and vice-versa. Point (D) is connected through R4 to C4 to point (A). Point (A) is the input to transistor Q1. By the same token, point (C), which is the output of Q1, is connected through R3 and C3 to the input (point (B)) of transistor Q2.

Taking a close look at the flip-flop circuit, you should be able to see how it maintains its stable condition. Typical values for the resistors and applied voltages are shown in figure 3-19. The capacitors have been removed for simplicity.

Figure 3-19 Flip-flop (capacitors removed)

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3-23 UNCLASSIFIED Two voltage-divider networks extend from -10 volts (VCC) to +6 volts (VBB). One voltage divider consisting of resistors R1, R4, and R6 supplies the bias voltage to the base of Q1. The other voltage divider consists of R2, R3, and R5 and supplies the bias voltage to the base of Q2.

Assume that Q1 (figure 3-20) is initially saturated and Q2 is cut off. Recall that the voltage drop from the base to the emitter of a saturated transistor is essentially 0 volts. In effect, this places the base of Q1 at ground potential. The voltages developed in the voltage divider, −VCC, R6, R4, R1, and +VBB, are shown in the figure.

Since no current flows through Q2, very little voltage is dropped across R6 (approximately 0.5 volt). The voltage at output 2 would measure -9.5 volts to ground (approximately −V CC).

This voltage (−9.5 volts) is considered to be a HIGH output. Figure 3-21 shows the values of the other voltage-divider network.

Figure 3-20 Flip-flop (Q1 voltage divider)

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With Q1 saturated, a large current flows through R5. The meter would measure approximately 0 volts (ground potential) at point (C). Notice that point (B) is located between point (C) (at 0 volts) and +V BB (at +6 volts). The meter would measure a positive voltage (between 0 volts and +6 volts) at the base of Q2 (point (B)).

A positive voltage on the base of a pnp transistor will cause that transistor to cut off. If one transistor is saturated, the other must be cut off. The flip-flop is stable in this state.

The capacitors that were removed from figure 3-19 must be returned to the flip-flop as shown in figure 3-22 to change the state of the flip-flop from one condition to the other. Capacitors C3 and C4 transmit almost instantaneously any changes in voltage from the collector of one transistor to the base of the other. Capacitors C1 and C2 are input coupling capacitors.

Figure 3-21 Flip-flop (Q2 voltage divider)

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As before, assume that transistor Q1 is saturated and transistor Q2 is cut off. Two methods are available to cause the flip-flop to change states. First, a positive-going pulse can be applied to input 1 to cause Q1 to change from saturation to cutoff. Second, the same result can be achieved by applying a negative-going pulse to input 2. Transistor Q2 would then change from Cutoff to saturation. Normally, a pulse is applied to the saturated transistor causing it to cut off. An input pulse which is of the correct polarity to change the state of the flip-flop is, as before, called a trigger pulse.

In figure 3-23 a positive-going trigger pulse has been applied to input 1. The flip-flop has now changed states; Q1 is cut off and Q2 is saturated. If a second positive-going trigger pulse is applied to input 1, it has no effect. This is because Q1 is already cut off; therefore, a positive pulse on its base has no effect. But if a positive-going trigger pulse were applied to input 2, the flip-flop would change back to its original state as shown in figure 3-24.

Figure 3-22 Flip-flop

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Figure 3-23 Bistable multivibrator (flip-flop) Figure 3-24 Flip-flop (original state)

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3-27 UNCLASSIFIED So far, the basic flip-flop has used only pnp transistors. It could have just as easily used npn transistors. The functional operation would not change; only the polarities required for conduction and cutoff change. As a technician, you may see either type of transistor used, npn or pnp. A symbolic block diagram is sometimes used to avoid confusion about voltage polarities.

A special kind of block diagram has been adopted as a standard symbol for the flip-flop and is shown in figures 3-25 and 3-26. The two inputs are represented by the lines on the left and the outputs by the lines on the right. INPUTS to a flip-flop are S (SET) and C (CLEAR) and OUTPUTS from a flip-flop are "1" and "0." A trigger pulse applied to the SET input causes the "1" output to be a positive or negative voltage, depending on the type of transistor. At the same time, the "0" output equals 0 volts. This condition is called the SET STATE.

If a trigger pulse is applied to the CLEAR input, a positive or negative voltage is produced at the "0" output. The "1" output goes to 0 volts. This condition is called the CLEAR STATE, as shown in figure 3-26.

Figure 3-25 Flip-flop (SET state) Figure 3-26 Flip-flop (CLEAR state)

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3-28 UNCLASSIFIED To determine what state the flip-flop is in, you can measure either the "1" or the "0" output. Measuring 0 volts at the "1" output indicates that the flip-flop is in the CLEAR state. If the "0" output is measured, a positive or negative voltage would also indicate that the flip-flop is in the CLEAR state. Either way, only one reading is necessary.

In figure 3-27, the flip-flop is in the SET state prior to T0 (negative voltage on the "1" output). Now compare the changes in output voltage at each point in time (T0, T1, T2, and T3) with the input pulse. Studying this figure should help you understand how the flip-flop works. The positive pulse at T0 on the CLEAR input shifts the f/f to the CLEAR state (negative voltage at the "0" output). At T1 a positive pulse on the SET input drives the "1" output to the SET state. At T2 a positive pulse on the CLEAR input drives the "0" output to a CLEAR state. At T3 another positive pulse is applied to the CLEAR input. This input has no effect since the f/f is already in the CLEAR state.

Some flip-flops use a third input lead, as shown in figure 3-28. This third input lead is called a TOGGLE (T) input. Every time a pulse is applied to the T input, the flip-flop will change states from whatever its state was previously. The two diodes (CR1, CR2) form a STEERING NETWORK. This steering network directs a positive input pulse to the saturated transistor, causing it to cut off. Negative pulses are blocked by the diodes. Note that if npn transistors were used, the diodes would have to be reversed and the TOGGLE signal would have to be negative. For example, assume that Q1 is saturated, Q2 is cut off, and a positive pulse is applied the at T input. The input pulse will be directed to both transistors. The positive pulse will not affect Q2 since it is already in cutoff. Q1 however, which is conducting, will cut off and will cause Q2 to become saturated. The transistors have reversed states. A block diagram which represents a multivibrator and its outputs with only a TOGGLE input signal is shown in figure 3-29. Studying this figure should help you understand how this flip-flop works. Each TOGGLE input causes the output to change states. Figure 3-30 shows what happens when triggers are applied to all three inputs of the flip-flop shown in figure 3-28. Assume that the flip-flop in figure 3-30 is in the CLEAR state ("1" output is 0 volts, "0" output is high) prior to T0. At T0 a trigger is applied to the set input and the flip-flop changes states.

Figure 3-27 Flip-flop with trigger pulse on SET and inputs

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3-29 UNCLASSIFIED Next, the CLEAR input is triggered and the flip-flop returns to the CLEAR state at T1. A TOGGLE at T2 causes the flip-flop to change state, so it is once again SET. Another TOGGLE changes the flip-flop to the CLEAR state at T3 (notice that TOGGLE triggers flip the multivibrator regardless of its previous state). Now, a SET input trigger at T4 sets the flip-flop. The CLEAR input pulse at T5 causes the circuit to CLEAR, and the CLEAR input at T6 has n o effect on the flip-flop, for it is already in the CLEAR state.

Figure 3-28 Flip-flop with three inputs Figure 3-29 Block diagram of a flip-flop with a toggle input

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Remember, a SET input will SET the flip-flop if it is in the CLEAR state, otherwise, it will not do anything; a trigger at the CLEAR input can only CLEAR the circuit if it is SET; and a trigger applied to the TOGGLE input will cause the bistable multivibrator to change states regardless of what state it is in.

Q7. In a bistable multivibrator, how many trigger pulses are needed to produce one complete cycle in the output? Q8. How many stable states are there for a flip-flop? Q9. If a voltage (positive or negative) is measured on the "1" output of a flip-flop, what state is it in? 3.2.2 Blocking Oscillator The BLOCKING OSCILLATOR is a special type of wave generator used to produce a narrow pulse, or trigger. Blocking oscillators have many uses, most of which are concerned with the timing of some other circuit. They can be used as frequency dividers or counter circuits and for switching other circuits on and off at specific times.

In a blocking oscillator the pulse width (pw), pulse repetition time (prt), and pulse repetition rate (prr) are all controlled by the size of certain capacitors and resistors and by the operating characteristics of the transformer. The transformer primary determines the duration and shape of the output. Because of their importance in the circuit, transformer action and series RL circuits will be discussed briefly. You may want to review transformer action in NEETS, Module 2, Alternating Current and Transformers before going to the next section.

Figure 3-30 Flip-flop with three inputs (block diagram)

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3-31 UNCLASSIFIED 3.2.2.1 Transformer Action Figure 3-31, view (A), shows a transformer with resistance in both the primary and secondary circuits. If S1 is closed, current will flow through R1 and L1. As the current increases in L1, it induces a voltage into L2 and causes current flow through R2. The voltage induced into L2 depends on the ratio of turns between L1 and L2 as well as the current flow through L1.

The secondary load impedance, R2, affects the primary impedance through reflection from secondary to primary. If the load on the secondary is increased (R2 decreased), the load on the primary is also increased and primary and secondary currents are increased.

T1 can be shown as an inductor and R1-R2 as a combined or equivalent series resistance (R E) since T1 has an effective inductance and any change in R1 or R2 will change the current. The equivalent circuit is shown in figure 3-31, view (B). It acts as a series RL circuit and will be discussed in those terms.

Figure 3-31A RL circuit

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3.2.2.2 Simple Series RL Circuit When S1 is closed in the series RL circuit (view (B) of figure 3-31) L acts as an open at the first instant as source voltage appears across it. As current begins to flow, E L decreases and ER and I increase, all at exponential rates. Figure 3-32, view (A), shows these exponential curves. In a time equal to 5 time constants the resistor voltage and current are maximum and EL is zero. This relationship is shown in the following formula:

Figure 3-31B.— RL circuit

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If S1 is closed, as shown in figure 3-31, view (B), the current will follow curve 1 as shown in figure 3-32, view (A). The time required for the current to reach maximum depends on the size of L and R E. If RE is small, then the RL circuit has a long time constant. If only a small portion of curve 1 (C to D of view (A)) is used, then the current increase will have maximum change in a given time period. Further, the smaller the time increment the more nearly linear is the current rise. A constant current increase through the coil is a key factor in a blocking oscillator.

3.2.2.3 Blocking Oscillator Applications A basic principle of inductance is that if the increase of current through a coil is linear; that is, the rate of current increase is constant with respect to time, then the induced voltage will be constant. This is true in both the primary and secondary of a transformer. Figure 3-32, view (B), shows the voltage waveform across the coil when the current through it increases at a constant rate. Notice that this waveform is similar in shape to the trigger pulse shown earlier in figure 3-1, view (E). By definition, a blocking oscillator is a special type of oscillator which uses inductive regenerative feedback.

Figure 3-32A Voltage across a coil

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3-34 UNCLASSIFIED The output duration and frequency of such pulses are determined by the characteristics of a transformer and its relationship to the circuit. Figure 3-33 shows a blocking oscillator. This is a simplified form used to illustrate circuit operation.

Figure 3-32B.— Voltage across a coil Figure 3-33 Blocking oscillator

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3-35 UNCLASSIFIED When power is applied to the circuit, R1 provides forward bias and transistor Q1 conducts. Current flow through Q1 and the primary of T1 induces a voltage in L2. The phasing dots on the transformer indicate a 180-degree phase shift. As the bottom side of L1 is going negative, the bottom side of L2 is going positive. The positive voltage of L2 is coupled to the base of the transistor through C1, and Q1 conducts more. This provides more collector current and more current through L1. This action is regenerative feedback. Very rapidly, sufficient voltage is applied to saturate the base of Q1. Once the base becomes saturated, it loses control over collector current. The circuit now can be compared to a small resistor (Q1) in series with a relatively large inductor (L1), or a series RL circuit.

The operation of the circuit to this point has generated a very steep leading edge for the output pulse. Figure 3-34 shows the idealized collector and base waveforms. Once the base of Q1 (figure 3-33) becomes saturated, the current increase in L1 is determined by the time constant of L1 and the total series resistance. From T0 to T1 in figure 3-34 the current increase (not shown) is approximately linear. The voltage across L1 will be a constant value as long as the current increase through L1 is linear.

Figure 3-34 Blocking oscillator idealized waveforms

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3-36 UNCLASSIFIED At time T1, L1 saturates. At this time, there is no further change in magnetic flux and no coupling from L1 to L2. C1, which has charged during time TO to T1, will now discharge through R1 and cut off Q1. This causes collector current to stop, and the voltage across L1 returns to 0.

The length of time between T0 and T1 (and T2 to T3 in the next cycle) is the pulse width, which depends mainly on the characteristics of the transformer and the point at which the transformer saturates. A transformer is chosen that will saturate at about 10 percent of the total circuit current. This ensures that the current increase is nearly linear. The transformer controls the pulse width because it controls the slope of collector current increase between points T0 and T1. Since TC = L ÷ R, the greater the L, the longer the TC. The longer the time constant, the slower the rate of current increase. When the rate of current increase is slow, the voltage across L1 is constant for a longer time. This primarily determines the pulse width.

From T1 to T2 (figure 3-34), transistor Q1 is held at cutoff by C1 discharging through R1 (figure 3-33). The transistor is now said to be "blocked." As C1 gradually loses its charge, the voltage on the base of Q1 returns to a forward-bias condition. At T2, the voltage on the base has become sufficiently positive to forward bias Q1, and the cycle is repeated.

The collector waveform may have an INDUCTIVE OVERSHOOT (PARASITIC OSCILLATIONS) at the end of the pulse. When Q1 cuts off, current through L1 ceases, and the magnetic field collapses, inducing a positive voltage at the collector of Q1. These oscillations are not desirable, so some means must be employed to reduce them. The transformer primary may be designed to have a high dc resistance resulting in a low Q; this resistance will decrease the amplitude of the oscillations. However, more damping may be necessary than such a low-Q transformer primary alone can achieve. If so, a DAMPING resistor can be placed in parallel with L1, as shown in figure 3-35.

Figure 3-35 Circuit damping

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3-37 UNCLASSIFIED When an external resistance is placed across a tank, the formula for the Q of the tank circuit is Q = R/XL, where R is the equivalent total circuit resistance in parallel with L. You should be able to see from the equation that the Q is directly proportional to the damping resistance (R). In figure 3-35, damping resistor R2 is used to adjust the Q which reduces the amplitude of overshoot parasitic oscillations. As R2 is varied from infinity toward zero, the decreasing resistance will load the transformer to the point that pulse amplitude, pulse width, and prf are affected. If reduced enough, the oscillator will cease to function. By varying R2, varying degrees of damping can be achieved, three of which are shown in figure 3-36, view (A), view (B and view (C).

Figure 3-36A Waveform damping. CRITICAL DAMPING

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3-38 UNCLASSIFIED

Figure 3-36B.— Waveform damping. UNDER DAMPING. Figure 3-36C.— Waveform damping. OVER DAMPING

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3-39 UNCLASSIFIED CRITICAL DAMPING gives the most rapid transient response without overshoot. This is accomplished by adjusting R2 to achieve a waveform as shown in figure 3-36, view (A). The resistance of R2 depends upon the Q of the transformer. View (A) shows that oscillations, including the overshoot, are damping out.

UNDERDAMPING gives rapid transient response with overshoot caused by high or infinite resistance as shown in figure 3-36, view (B). OVERDAMPING is caused by very low resistance and gives a slow transient response. It may reduce the pulse amplitude as shown in figure 3-36, view (C).

The blocking oscillator discussed is a free-running circuit. For a fixed prf, some means of stabilizing the frequency is needed. One method is to apply external synchronization triggers (figure 3-37), view (A) and view (B). Coupling capacitor C2 feeds input synchronization (sync) triggers to the base of Q1.

Figure 3-37A Blocking oscillator (synchronized)

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If the trigger frequency is made slightly higher than the free-running frequency, the blocking oscillator will "lock in" at the higher frequency. For instance, assume the free- running frequency of this blocking oscillator is 2 kilohertz, with a prt of 500 microseconds. If sync pulses with a prt of 400 microseconds, or 2.5 kilohertz, are applied to the base, the blocking oscillator will "lock in" and run at 2.5 kilohertz. If the sync prf is too high, however, frequency division will occur. This means that if the sync prt is too short, some of the triggers occur when the base is far below cutoff. The blocking oscillator may then synchronize with every second or third sync pulse.

For example, in figure 3-37, view (A) and view (B) if trigger pulses are applied every 200 microseconds (5 kilohertz), the trigger that appears at T1 is not of sufficient amplitude to overcome the cutoff bias and turn on Q1. At T2, capacitor C1 has nearly discharged and the trigger causes Q1 to conduct. Note that with a 200-microsecond input trigger, the output prt is 400 microseconds. The output frequency is one-half the input trigger frequency and the blocking oscillator becomes a frequency divider.

Q10. What component in a blocking oscillator controls pulse width?

Figure 3-37B.— Blocking oscillator (synchronized)

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3-41 UNCLASSIFIED 3.2.3 Time-Base Generators Radar sets, oscilloscopes, and computer circuits all use sawtooth (voltage or current) waveforms. A sawtooth waveshape must have a linear rise. The sawtooth waveform is often used to produce a uniform, progressive movement of an electron beam across the face of an electrostatic cathode ray tube. This movement of the electron beam is known as a SWEEP. The voltage which causes this movement is known as SWEEP VOLTAGE and the circuit which produces this voltage is the SWEEP GENERATOR, or TIME- BASE GENERATOR. Most common types of time-base generators develop the sawtooth waveform by using some type of switching action with either the charge or discharge of an RC or RL circuit.

3.2.3.1 Sawtooth Wave A sawtooth wave can be generated by using an RC network. Possibly the simplest sawtooth generator is that which is shown in figure 3-38, view (A). Assume that at T0 (view (B)). S1 is placed in position P. At the instant the switch closes, the applied voltage (Ea) appears at R. C begins to charge to Ea through R. If S1 remains closed long enough, C will fully charge to Ea. You should remember from NEETS, Module 2, Alternating Current and Transformers, that a capacitor takes 5 time constants (5TC) to fully charge. As the capacitor charges to the applied voltage, the rate of charge follows an exponential curve. If a linear voltage is desired, the full charge time of the capacitor cannot be used because the exponential curve becomes nonlinear during the first time constant.

Figure 3-38A Series RC circuit

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3-42 UNCLASSIFIED

However, during the first 10 percent of the first time constant, the rate of voltage change across the capacitor is almost constant (linear). Suppose that S1 is placed in position P at T0, and C is allowed to charge for 0.1 time constant. This is shown as T0 to T1 in view (B). Notice that the rate of voltage change across C is nearly constant between T0 and T1. Now, assume that at T1 the switch is moved from position P to position Q. This shorts the capacitor, and it discharges very rapidly. If the switch is placed back in position P, the capacitor will start charging again.

By selecting the sizes of R and C, you can have a time constant of any value you desire. Further, by controlling the time S1 remains closed, you can generate a sawtooth of any duration. Figure 3-39 is the Universal Time Constant Chart. Notice in the chart that if 1 time constant is 1,000 microseconds, S1 (figure 3-38, view (A)) can be closed no longer than 100 microseconds to obtain a reasonable linear sawtooth. In this example, C1 will charge to nearly 10 volts in 0.1 time constant.

Figure 3-38B.—Series RC circuit

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The dimensions of the sawtooth waveform used in oscilloscopes need to be discussed before going any further. Figure 3-40 shows a sawtooth waveform with the various dimensions labeled. The duration of the rise of voltage (T0 to T1) is known as the SWEEP TIME or ELECTRICAL LENGTH. The electron beam of an oscilloscope moves across the face of the cathode ray tube during this sweep time. The amount of voltage rise per unit of time is referred to as the SLOPE of the waveform. The time from T1 to T2 is the capacitor discharge time and is known as FALL TIME or FLYBACK TIME. This discharge time is known as flyback time because during this period the electron beam returns, or "flys" back, from the end of a scanning line to begin the next line.

Figure 3-39 Universal Time Constant Chart

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The amplitude of the rise of voltage is known as the PHYSICAL LENGTH. It is called physical length because the greater the peak voltage, the greater physical distance the beam will move. For example, the amount of voltage needed to move an electron beam 4 inches is twice the amount needed to move the beam 2 inches across the face of a given crt.

The voltage rise between T0 to T1 is the LINEAR SLOPE of the wave. The linearity of the rise of voltage is determined by the amount of time the capacitor is allowed to charge. If the charge time is kept short (10 percent or less of 1TC), the linearity is reasonably good.

As stated in the discussion of time-base generators, the waveform produced from any sawtooth generator must be linear. A LINEAR SAWTOOTH is one that has an equal change in voltage for an equal change in time. Referring to the Universal Time Constant Chart in figure 3-39, you can see that the most desirable part of the charge curve is the first one-tenth (0.1) of the first TC.

Figure 3-40 Sawtooth waveform

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3-45 UNCLASSIFIED Figure 3-41, view (A), is a transistor sawtooth generator. In this figure R1 is a forward- biasing resistor for Q1, C1 is a coupling capacitor, and Q1 is serving as a switch for the RC network consisting of R2 and C2. With forward bias applied to Q1, the generator conducts at saturation, and its collector voltage (the output) is near 0 volts as indicated by the waveform in view (B). The charge felt by C1 is nearly 0. A negative gate is applied to the base of Q1 to cut off Q1 and allow C2 to charge. The length of time that the gate is negative determines how long Q1 will remain cut off and, in turn, how long C2 will be allowed to charge. The length of time that C2 is allowed to charge is referred to as the electrical length of the sawtooth that is produced.

Figure 3-41A Transistor sawtooth generator

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The amplitude of the sawtooth that is produced is limited by the value of V CC that is used in the circuit. For example, if the voltage is 30 volts, and the capacitor (C2) is allowed to charge to 10 percent of 30 volts, then the amplitude of the sawtooth will be 3 volts (see figure 3-41, view (B)). If VCC is increased to 40 volts, C2 will charge to 10 percent of 40 volts and the output will increase in amplitude to 4 volts.

Changing the value of V CC in the circuit changes the amplitude of the sawtooth waveform that is produced; amplitude determines the physical length. Since the number of time constants used in the circuit has not been changed, linearity does not change with a change in VCC.

The linear slope that is produced by the circuit is dependent on two variables; (1) the time constant of the RC circuit and (2) the gate length of the gate applied to the circuit. The circuit will produce a linear sawtooth waveshape if the components selected are such that only one-tenth of 1 TC or less is used. The GATE LENGTH is the amount of time that the gate is applied to the circuit and controls the time that the capacitor is allowed to charge. The value of R2 and C2 determines the time for 1 time constant (TC = RC). To determine the number of time constants (or the fraction of 1TC) used, divide the time for 1 time constant into the time that the capacitor is allowed to charge:

Figure 3-41B.—Transistor sawtooth generator

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3-47 UNCLASSIFIED In figure 3-41, view (B), gate length is 500 microseconds and TC is the product of R2 (5 kilohms) and C2 (1 microfarad). The number of time constants is computed as follows:

Therefore, 0.1TC is the length of time required to produce a linear rise in the sawtooth waveform.

shows that an increase in gate length increases the number of time constants. An increase in the number of time constants decreases linearity. The reason is that C2 now charges to a greater percentage of the applied voltage, and a portion of the charge curve is being used that is less linear. The waveform in figure 3-42, view (A), shows an increase in amplitude (physical length), an increase in the time that C2 is allowed to charge (electrical length), and a decrease in linearity. If a smaller percentage of V CC is used, the gate length is decreased. As shown in view (B), this decreased gate length results in an increase in linearity, a decrease in the time that C2 is allowed to charge (electrical length), and a decrease in amplitude (physical length).

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3-48 UNCLASSIFIED

Figure 3-42A Relationship of gate to linearity Figure 3-42B.— Relationship of gate to linearity

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3-49 UNCLASSIFIED Changing the value of R and C in the circuit affects linearity since they control the time for 1 time constant. For example, if the value of C2 is increased in the circuit, as shown in figure 3-43, view (A), the time for 1 time constant increases and the number of time constants then decreases. With a decrease in the number of time constants, linearity increases. The reason is that a smaller percentage of VCC is used, and the circuit is operating in a more linear portion of the charge curve. Increasing the value of the TC (C2 or R2) decreases the amplitude of the sawtooth (physical length) because C2 now charges to a smaller percentage V CC for a given time. The electrical length remains the same because the length of time that C2 is allowed to charge has not been changed.

Figure 3-43A Relationship of R and C to linearity

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\ Decreasing the value of the TC (R2 or C2), as shown in figure 3-43, view (B), results in an increase in the number of time constants and therefore causes linearity to decrease. Anytime the number of time constants increases, the percentage of charge increases (see the Universal Time Constant Chart, figure 3-39), and amplitude (physical length) increases. Without an increase in gate length, the time that C2 is allowed to charge through R2 remains the same; therefore, electrical length remains the same. Linearity is affected by gate length, the value of R, and the value of C; but is not affected by changing the value of V CC. Increasing the gate length decreases linearity, and decreasing gate length increases linearity. Increasing R or C in the circuit increases linearity, and decreasing R or C in the circuit decreases linearity.

The entire time of the sawtooth, from the time at which the capacitor begins charging (T0 in figure 3-41, view (B)) to the time when it starts charging again (T2), is known as the prt of the wave. The pulse repetition frequency of the sawtooth wave is:

Figure 3-43B.—Relationship of R and C to linearity

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3-51 UNCLASSIFIED 3.2.3.2 Unijunction Sawtooth Generator. So far, you have learned in this chapter that a switch and an RC network can generate a sawtooth waveform. When using a unijunction transistor as the switch, a simple sawtooth generator looks like the circuit in figure 3-44, view (A); the output waveshapes are shown in view (B). You may want to review unijunction transistors in NEETS, Module 7, Solid- State Devices and Power Supplies, chapter 3, before continuing.

When the 20 volts is applied across B2 and B1, the n-type bar acts as a voltage- divider. A voltage of 12.8 volts appears at a point near the emitter. At the first instant, C1 has no voltage across it, so the output of the circuit, which is taken across the capacitor (C1), is equal to 0 volts. (The voltage across C1 is also the voltage that is applied to the emitter of the unijunction.) The unijunction is now reverse biased. After T0, C1 begins to charge toward 20 volts.

At T1, the voltage across the capacitor (the voltage on the emitter) has reached approximately 12.8 volts. This is the peak point for the unijunction, and it now becomes forward biased. With the emitter forward biased, the impedance between the emitter and B1 is just a few ohms. This is similar to placing a short across the capacitor. The capacitor discharges very rapidly through the low resistance of B1 to E.

Figure 3-44A Unijunction sawtooth generator. SCHEMATIC

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3-52 UNCLASSIFIED As C1 discharges, the voltage from the emitter to B1 also decreases. Q1 will continue to be forward biased as long as the voltage across C1 is larger than the valley point of the unijunction.

At T2 the 3-volt valley point of the unijunction has been reached. The emitter now becomes reverse biased and the impedance from the emitter to B1 returns to a high value. Immediately after T2, Q1 is reverse biased and the capacitor has a charge of approximately 3 volts. C1 now starts to charge toward 20 volts as it did originally (just after T0). This is shown from T2 to T3 in figure 3-44, view (B).

Figure 3-44B.— Unijunction sawtooth generator. EMITTER WAVEFORM

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3-53 UNCLASSIFIED The circuit operation from now on is just a continuous repetition of the actions between T2 and T4. The capacitor charges until the emitter becomes forward biased, the unijunction conducts and C1 discharges, and Q1 becomes reverse biased and C1 again starts charging.

Now, let's determine the linearity, electrical length, and amplitude of the output waveform. First, the linearity: To charge the circuit to the full 20 volts will take 5 time constants. In the circuit shown in figure 3-44, view (B), C1 is allowed to charge from T2 to T3. To find the percentage of charge, use the equation:

This works out to be about 57 percent and is far beyond the 10 percent required for a linear sweep voltage. The linearity is very poor in this example.

The electrical length (sweep time), which is measured from T2 to T3, can be found by multiplying RC times the number of time constants. Refer to the Universal Time Constant Chart (figure 3-39) again to find that 57 percent is 0.83TC. By multiplying 0.83 times R1C1, you will find that the electrical length is approximately 21 milliseconds:

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3-54 UNCLASSIFIED The physical length (amplitude) is determined by subtracting the valley point from the peak point. This is 9.8 volts in the example (12.8 volts − 3 volts).

For a sweep generator that produces a more linear output sawtooth waveform, refer to the circuit in figure 3-45, view (A). R1 and C1 form the RC time constant. Notice that the capacitor charges toward 35 volts (V E) in this circuit.

Figure 3-45A Improved unijunction sawtooth generator Figure 3-45B.— Improved unijunction sawtooth generator

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3-55 UNCLASSIFIED The output waveform is shown in figure 3-45, view (B). With a lower voltage applied from B1 to B2, the peak and valley points are closer together. Calculating the percentage of charge:

The linearity in this case is good. Using the Universal Time Constant Chart, a 10-percent charge amounts to 0.1 time constant. The electrical length is, again, RC times the number of time constants. With R1 at 300 kilohms and C1 at .005 microfarads, the time constant is 1,500 microseconds. One-tenth of a time constant is equal to 150 microseconds; so the electrical length is 150 microseconds. Prt is the electrical length plus the fall or flyback time. If C1 discharges from 5.3 volts to 2 volts in 15 microseconds, then the prt is 150 + 15, or 165 microseconds. The prf is about 6 kilohertz.

Some unijunction circuits are triggered to obtain a very stable prf. One method is to apply triggers to B2, as shown in figure 3-46. Negative triggers applied to B2 reduce the inter- base voltage enough to cause a forward bias condition in the emitter circuit. This cuts off the sweep and allows C1 to discharge through the B1-to-emitter circuit. Then, C1 recharges until the next trigger arrives and C1 discharges. Circuit operation and parameters are figured in the same manner as in the previous sawtooth circuits.

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3.2.3.3 Transistor Sawtooth Generator. The next sawtooth generator uses a conventional pnp transistor, as shown in figure 3-47, view (A). This generator also uses an RC network, and the transistor provides the switching action.

Figure 3-46 Synchronized sawtooth generator Figure 3-47A Transistor sawtooth generator (pnp)

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3-57 UNCLASSIFIED The waveforms for the circuit are shown in views (B) and (C). With no input signals, Q1 is biased near saturation by R1. The voltage across C1 is very low (-2.5 volts) because load resistor R3 drops most of the applied voltage. The transistor must be cut off to allow C1 to charge. To cut off Q1, a positive rectangular wave is used.

Figure 3-47B.—Transistor sawtooth generator (pnp) Figure 3-47C.—Transistor sawtooth generator (pnp)

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3-58 UNCLASSIFIED Since Q1 is a pnp transistor, a positive voltage must be used to drive it to cutoff. Figure 3-47, view (B), shows a rectangular wave input 500 microseconds long on the positive alternation. At T0, the positive gate applied to the base of Q1 cuts off Q1. This effectively removes the transistor from the circuit (opens the switch), and C1 charges through R3 toward 20 volts. Starting with a charge of −2.5 volts at T0, C1 charges (T0 to T1) for 500 microseconds to -4.25 volts at T1. Let's determine the percent of charge:

This allows nearly a linear rise of voltage across C1.

Increasing the value of R3 or C1 increases the time constant. The capacitor will not charge to as high a voltage in the same period of time. Decreasing the width of the gate and maintaining the same time constant also prevents the capacitor from charging as much. With less charge on the capacitor, and the same voltage applied, linearity has been improved. Decreasing R3 or C1 or increasing gate width decreases linearity. Changing the applied voltage will change the charge on the capacitor. The percentage of charge remains constant; however, it does not affect linearity.

At T1, the positive alternation of the input gate ends, and Q1 returns to a forward-bias condition. A transistor that is near saturation has very low resistance, so C1 discharges rapidly between T1 and T2, as shown in figure 3-47, view (C). The capacitor discharges in less than 200 microseconds, the length of the negative alternation of the gate. The negative gate is made longer than the discharge time of the capacitor to ensure that the circuit has returned to its original condition.

From T1 to T2, the capacitor discharges and the circuit returns to its original condition, ready for another positive gate to arrive. The next positive gate arrives at T2 and the actions repeats.

NEETS MODULE 9-Wave Generation and Wave Shaping UNCLASSIFIED

3-59 UNCLASSIFIED The amplitude of the output sawtooth wave is equal to 1.75 volts (4.25 volts minus 2.5 volts). The electrical length is the same as the positive alternation of the input gate, or 500 microseconds. The prt is 700 microseconds (500 + 200) and the prf is 1/prt or 1,428 hertz.

3.2.3.4 Trapezoidal Sweep Generator Normally, oscilloscopes and synchroscopes use ELECTROSTATIC DEFLECTION and, as the name implies, electrostatic fields move the electron beam. The need here is for a sawtooth voltage waveform.

Another method of electron beam deflection is ELECTROMAGNETIC DEFLECTION. Currents through a coil produce electromagnetic fields which position the beam of electrons. The electromagnetic system requires a sawtooth of current which increases at a linear rate. Because of the inherent characteristics of a coil, a sawtooth voltage does not cause a linear increase of current. A linear increase of current requires a TRAPEZOIDAL voltage waveform applied to a coil. This section discusses the generation of a trapezoidal wave.

Figure 3-48 shows a trapezoidal wave. The wave consists of a sharp, almost instantaneous jump in voltage followed by a linear rise to some peak value. The initial change in voltage at T0 is called a JUMP or STEP. The jump is followed by a linear sawtooth voltage rise. The time from the jump to the peak amplitude is the sum of the jump voltage and the sawtooth peak; where the peak value occurs is the electrical length. The peak voltage amplitude is the sum of the jump voltage and the sawtooth peak voltage. The waveshape can be considered a combination of a rectangular wave and a sawtooth wave.

Figure 3-48 Trapezoidal waveform

NEETS MODULE 9-Wave Generation and Wave Shaping UNCLASSIFIED

3-60 UNCLASSIFIED The inductance and resistance of a coil form a series RL circuit. The voltage drop across this inductance and resistance must be added to obtain the voltage waveform required to produce a linear rise in current. A linear rise of current produces a linear rise of voltage across the resistance of the coil and a constant voltage drop across the inductance of the coil.

Assume figure 3-49, view (A), represents deflection coils. If we apply a voltage waveshape to the circuit, which will provide a square wave across inductor L, and a sawtooth across resistor R, then a linear current rise will result.

View (B) of figure 3-49 shows the waveforms when E a is a square wave. Recall that the inductor acts as an open circuit at this first instant. Current now starts to flow and develops a voltage across the resistor. With a square wave applied, the voltage across the inductor starts to drop as soon as any voltage appears across the resistor. This is due to the fact that the voltage across the inductor and resistor must add up to the applied voltage.

Figure 3-49A Series LR circuit Figure 3-49B.—Series LR circuit

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3-61 UNCLASSIFIED With Ea being a trapezoidal voltage, as shown in figure 3-49, view (C), the instant current flows, a voltage appears across the resistor, and the applied voltage increases. With an increasing applied voltage, the inductor voltage remains constant (EL) at the jump level and circuit current (IR) rises at a linear rate from the jump voltage point. Notice that if you add the inductor voltage (EL) and resistor voltage (ER) at any point between times T0 and T1, the sum is the applied voltage (Ea). The key fact here is that a trapezoidal voltage must be applied to a sweep coil to cause a linear rise of current. The linear rise of current will cause a uniform, changing magnetic field which, in turn, will cause an electron beam to move at a constant rate across a crt.

There are many ways to generate a trapezoidal waveshape. For example, the rectangular part could be generated in one circuit, the sawtooth portion in another, and the two combined waveforms in still a third circuit. A far easier, and less complex, way is to use an RC circuit in combination with a transistor to generate the trapezoidal waveshape in one stage.

Figure 3-50, view (A), shows the schematic diagram of a trapezoidal generator. The waveshapes for the circuit are shown in view (B). R1 provides forward bias for Q1 and, without an input gate, Q1 conducts very hard (near saturation), C1 couples the input gate signal to the base of Q1. R2, R3, and C2 form the RC network which forms the trapezoidal wave. The output is taken across R3 and C2.

Figure 3-49C.— Series LR circuit

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3-62 UNCLASSIFIED

Figure 3-50A Trapezoidal waveform generator Figure 3-50B.—Trapezoidal waveform generator

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3-63 UNCLASSIFIED With Q1 conducting very hard, collector voltage is near 0 volts prior to the gate being applied. The voltage across R2 is about 50 volts. This means no current flows across R3, and C2 has no charge.

At T0, the negative alternation of the input gate is applied to the base of Q1, driving it into cutoff. At this time the transistor is effectively removed from the circuit. The circuit is now a series-RC network with 50 volts applied. At the instant Q1 cuts off, 50 volts will appear across the combination of R2 and R3 (the capacitor being a short at the first instant). The 50 volts will divide proportionally, according to the size of the two resistors. R2 then will have 49.5 volts and R3 will have 0.5 volt. The 0.5 volt across R3 (jump resistor) is the amplitude of the jump voltage. Since the output is taken across R3 and C2 in series, the output "jumps" to 0.5 volt.

Observe how a trapezoidal generator differs from a sawtooth generator. If the output were taken across the capacitor alone, the output voltage would be 0 at the first instant. But splitting the R of the RC network so that the output is taken across the capacitor and part of the total resistance produces the jump voltage.

Refer again to figure 3-50, view (A) and view (B). From T0 to T1, C2 begins charging toward 50 volts through R2 and R3. The time constant for this circuit is 10 milliseconds. If the input gate is 1,000 microseconds, the capacitor can charge for only 10 percent of 1TC, and the sawtooth part of the trapezoidal wave will be linear.

At T1, the input gate ends and Q1 begins to conduct heavily. C2 discharges through R3 and Q1. The time required to discharge C2 is primarily determined by the values of R3 and C2. The minimum discharge time (in this circuit) is 500 microseconds (5K x .02μF x 5). At T2, the capacitor has discharged back to 0 volts and the circuit is quiescent. It remains in this condition until T3 when another gate is applied to the transistor.

The amplitude of the jump voltage was calculated to be 0.5 volt. The sawtooth portion of the wave is linear because the time, T0 to T1, is only 10 percent of the total charge time. The amplitude of the trapezoidal wave is approximately 5 volts. The electrical length is the same as the input gate length, or 1,000 microseconds. Linearity is affected in the same manner as in the sawtooth generator. Increasing R2 or C2, or decreasing gate width, will improve linearity. Changing the applied voltage will increase output amplitude, but will not affect linearity.

Linearity of the trapezoidal waveform, produced by the circuit in figure 3-50, view (A) and view (B) depends on two factors, gate length and the time constant of the RC circuit. Recall that these are the same factors that controlled linearity in the sawtooth generator. The formula developed earlier still remains true and enables us to determine what effect these factors have on linearity.

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3-64 UNCLASSIFIED

An increase in gate length results in an increase in the number of time constants and an increase in the percentage of charge that the capacitor will take on during this time interval. As stated earlier, if the number of time constants were to exceed 0.1, linearity would decrease. The reason for a decrease in linearity is that a greater percentage of V CC is used. The Universal Time Constant Chart (figure 3-39) shows that the charge line begins to curve. A decrease in gate length has the opposite effect on linearity in that it causes linearity to increase. The reason for this increase is that a smaller number of time constants are used and, in turn, a smaller percentage of the applied V CC is used.

Changing the value of resistance or capacitance in the circuit also affects linearity. If the value of C2 or R3 is increased, the time is increased for 1 time constant. An increase in the time for 1TC results in a decrease in the number of time constants required for good linearity. As stated earlier, a decrease in the number of time constants results in an increase in linearity (less than 0.1TC). In addition to an increase in jump voltage (larger value of R3) and a decrease in the amplitude (physical length) of the sawtooth produced by the circuit, electrical length remains the same because the length of the gate was not changed.

R2 has a similar effect on linearity because it is in series with R3. As an example, decreasing the value of R2 results in a decrease in linearity. The equation

illustrates that by decreasing R (TC = RC), TC decreases and an increase in the number of time constants causes a decrease in linearity. Other effects are an increase in jump voltage and an increase in the amplitude (physical length) of the sawtooth.

Changing the value of V CC does not affect linearity. Linearity is dependent on gate length, R, and C. VCC does affect the amplitude of the waveform and the value of jump voltage that is obtained.

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3-65 UNCLASSIFIED Q11. For an RC circuit to produce a linear output across the capacitor, the voltage across the capacitor may not exceed what percent of the applied voltage? Q12. Increasing gate length in a sawtooth generator does what to linearity? Q13. In a sawtooth generator, why is the transistor turned on for a longer time than the discharge time of the RC network? Q14. What is added to a sawtooth generator to produce a trapezoidal wave? 3.3 SUMMARY This chapter has presented information on waveforms and wave generators. The information that follows summarizes the important points of this chapter.

A waveform which undergoes a pattern of changes, returns to its original pattern, and repeats that same pattern of changes is called a PERIODIC waveform.

Each completed pattern of a waveform is called a CYCLE.

A SQUARE WAVE is identified by, two alternations equal in time that are square in appearance. One alternation is called a PULSE. The time for one complete cycle is called the PULSE REPETITION TIME (prt). The number of times in one second that the cycle repeats itself is called PULSE REPETITION RATE (prr) or PULSE REPETITION FREQUENCY (prf). The length of the pulse measured in the figure (T0 to T1) is referred to as the PULSE WIDTH (pw). The left side of the pulse is referred to as the LEADING EDGE and the right side as the TRAILING EDGE.

A RECTANGULAR WAVE has two alternations that are unequal in time.

A SAWTOOTH WAVE has a linear increase in voltage followed by a rapid decrease of voltage at the end of the waveform.

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3-66 UNCLASSIFIED A TRAPEZOIDAL WAVE looks like a sawtooth wave sitting on top of a square wave. The leading edge is called the JUMP voltage.

A TRIGGER is a very narrow pulse used to turn on or off another circuit.

A MULTIVIBRATOR is used to generate a square or rectangular wave. A multivibrator is basically two amplifiers with regenerative feedback.

The ASTABLE MULTIVIBRATOR has no stable state. The transistors alternately switch from cutoff to saturation at a frequency determined by the RC time constants of the coupling circuits.

The MONOSTABLE MULTIVIBRATOR has one stable state. One transistor conducts while the other is cut off. An external trigger must be applied to change this condition.

The BISTABLE MULTIVIBRATOR has two steady states. It remains in one of the stable states until a trigger is applied. It then switches to the other stable state until another trigger is applied.

The bistable multivibrator is also known as a FLIP-FLOP. The two inputs are SET and CLEAR. The two outputs are "1" and "0." A trigger pulse on the set input will cause the "1" output (negative or positive voltage depending on the type transistor used). At the same time the "0" output will equal 0 volts. This is the SET state.

A CLEAR STATE of a flip-flop exists when the "1" output measures low voltage (or 0 volts) and the "0" output is high voltage. The flip-flop will flop to the CLEAR state only upon application of a trigger pulse to the CLEAR (C) input.

There is a third lead on some flip-flops. This lead is the TOGGLE (T) input. Every time a trigger pulse is applied to the (T) input, the flip-flop will change states.

BLOCKING OSCILLATORS are used in applications which require a narrow pulse with sharp leading and trailing edges. They are used as TRIGGER GENERATORS or FREQUENCY DIVIDERS.

A SAWTOOTH GENERATOR voltage waveform has a linear change in voltage and a fast recovery time. The linear change in voltage is generated by taking the output from a capacitor. The sawtooth voltage waveform is used to provide electrostatic deflection in oscilloscopes.

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3-67 UNCLASSIFIED A TRAPEZOIDAL GENERATOR voltage waveform is used to provide, a linear increase in current through a coil. A trapezoidal wave begins with a step or jump voltage, then a sawtooth wave. A trapezoidal wave of voltage is used in electromagnetic deflection display devices.

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3-68 UNCLASSIFIED ANSWERS TO QUESTIONS Q1. THROUGH Q14. A1. Multivibrator.

A2. Astable.

A3. Monostable.

A4. Bistable.

A5. RC coupling networks.

A6. One-shot.

A7. Two.

A8. Two.

A9. SET state.

A10. Transformer.

A11. Ten percent.

A12. Decreases linearity.

A13. To allow the capacitor time to discharge.

A14. A resistor.

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4-1 UNCLASSIFIED 4 WA VE SHAPING LEARNING OBJECTIVES After you finish this chapter, you should be able to do the following: 1. Explain the operation of series-limiter circuits. 2. Explain the operation of parallel-limiter circuits. 3. Describe the operation of a dual-diode limiter circuit. 4. Explain the operation of clamper circuits. 5. Explain the composition of nonsinusoidal waves. 6. Explain how RC and RL circuits are used as integrators. 7. Explain how RC and RL circuits are used as differentiators. 8. Explain the operation of a counting circuit. 9. Explain the operation of a step-by-step counter used as a frequency divider.

4.1 LIMITERS As a technician, you will be confronted with many different types of LIMITING circuits. A LIMITER is defined as a device which limits some part of a waveform from exceeding a specified value. Limiting circuits are used primarily for wave shaping and circuit- protection applications.

A limiter is little more than the half-wave rectifier you studied in NEETS, Module 6, Electronic Emission, Tubes, and Power Supplies. By using a diode, a resistor, and sometimes a dc bias voltage, you can build a limiter that will eliminate the positive or negative alternations of an input waveform. Such a circuit can also limit a portion of the alternations to a specific voltage level. In this chapter you will be introduced to five types of limiters: SERIES-POSITIVE, SERIES-NEGATIVE, PARALLEL-POSITIVE, PARALLEL-NEGATIVE, and DUAL-DIODE LIMITERS. Both series- and parallel- positive and negative limiters use biasing to obtain certain wave shapes. They will be discussed in this chapter.

The diode in these circuits is the voltage-limiting component. Its polarity and location, with respect to ground, are the factors that determine circuit action. In series limiters, the diode is in series with the output. In parallel limiters, the diode is in parallel with the output.

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4-2 UNCLASSIFIED 4.1.1 Series Limiters You should remember, from NEETS, Module 7, Solid-State Devices and Power Supplies, that a diode will conduct when the anode voltage is positive with respect to the cathode voltage. The diode will not conduct when the anode is negative in respect to the cathode. Keeping these two simple facts in mind as you study limiters will help you understand their operation. Your knowledge of voltage divider action from NEETS, Module 1, Matter, Energy, and Direct Current will also help you understand limiters.

In a SERIES LIMITER, a diode is connected in series with the output, as shown in view (A) of figure 4-1. The input signal is applied across the diode and resistor and the output is taken across the resistor. The series-limiter circuit can limit either the positive or negative alternation, depending on the polarity of the diode connection with respect to ground. The circuit shown in figure 4-1, view (B), is a SERIES-POSITIVE LIMITER. Reversing D1 would change the circuit to a SERIES-NEGATIVE LIMITER.

Figure 4-1A Series-positive limiter Figure 4-1B.—Series -positive limiter

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4-3 UNCLASSIFIED 4.1.1.1 Series-Positive Limiter Let's look at the series-positive limiter and its outputs in figure 4-1. Diode D1 is in series with the output and the output is taken across resistor R1. The input must be negative with respect to the anode of the diode to make the diode conduct. When the positive alternation of the input signal (T0 to T1) is applied to the circuit, the cathode is positive with respect to the anode. The diode is reverse biased and will not conduct. Since no current can flow, no output is developed across the resistor during the positive alternation of the input signal.

During the negative half cycle of the input signal (T1 to T2), the cathode is negative with respect to the anode. This causes D1 to be forward biased. Current flows through R1 and an output is developed.

The output during each negative alternation of the input is approximately the same as the input (−10 volts) because most of the voltage is developed across the resistor.

Ideally, the output wave shape should be exactly the same as the input wave shape with only the limited portion removed. When the diode is reverse biased, the circuit has a small amount of reverse current flow, as shown just above the 0-volt reference line in figure 4-2. During the limiting portion of the input signal, the diode resistance should be high compared to the resistor. During the time the diode is conducting, the resistance of the diode should be small as compared to that of the resistor. In other words, the diode should have a very high front-to-back ratio (forward resistance compared to reverse resistance). This relationship can be better understood if you study the effects that a front- to-back resistance ratio has on circuit output.

Figure 4-2 Actual output of a series-positive limiter

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4-4 UNCLASSIFIED The following formula can be used to determine the output amplitude of the signal:

Let's use the formula to compare the front-to-back ratio of the diode in the forward- and reverse-biased conditions.

Given:

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4-5 UNCLASSIFIED

You can readily see that the formula comparison of the forward- and reverse-bias resistance conditions shows that a small amount of reverse current will flow during the limited portion of the input waveform. This small amount of reverse current will develop as the small positive voltage (0.09 volt) shown in figure 4-2 (T0 to T1 and T2 to T3). The actual amount of voltage developed will depend on the type of diode used. For the remainder of this chapter, we will use only idealized waveforms and disregard this small voltage.

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4-6 UNCLASSIFIED SERIES-POSITIVE LIMITER WITH BIAS.— In the series-positive limiter (figure 4-1, view (A)), the reference point at the bottom of resistor R1 is ground, or 0 volts. By placing a dc potential at point (1) in figure 4-3 (views (A) and (B)), you can change the reference point. The reference point changes by the amount of dc potential that is supplied by the battery. The battery can either aid or oppose the flow of current in the series-limiter circuit. POSITIVE BIAS (aiding) is shown in view (A) and NEGATIVE BIAS (opposing) is shown in view (B).

Figure 4-3A Positive and negative bias. POSITIVE BIAS Figure 4-3B.— Positive and negative bias. NEGATIVE BIAS

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4-7 UNCLASSIFIED When the dc aids forward bias, as in view (A), the diode conducts even with no signal applied. An input signal sufficiently positive to overcome the dc bias potential is required to reverse bias and cut off the diode.

Let's look at a series-positive limiter with positive bias as shown in figure 4-4, views (A) and (B). The diode will conduct until the input signal exceeds +5 at T1 on the positive alternation of the input signal. When the positive alternation exceeds +5 volts, the diode becomes reverse biased and limits the positive alternation of the output signal to +5 volts. This is because there is no current flow through resistor R1 and battery voltage is felt at point (B). The diode will remain reverse biased until the positive alternation of the input signal decreases to just under +5 volts at T2. At this time, the diode again becomes forward biased and conducts. The diode will remain forward biased from T2 to T3. During this period the negative alternation of the input is passed through the diode without being limited. From T3 to T4 the diode is again reverse biased and the output is again limited.

Figure 4-4A Series-positive limiter with positive bias Figure 4-4B.— Series-positive limiter with positive bias

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4-8 UNCLASSIFIED Now let's look at what takes place when reverse bias is aided, as shown in figure 4-5, view (A). The diode is negatively biased with -5 volts from the battery. In view (B), compare the output to the input signal applied. From T0 to T1 the diode is reverse biased and limiting takes place. The output is at -5 volts (battery voltage) during this period. As the negative alternation increases toward -10 volts (T1), the cathode of the diode becomes more negative than the anode and is forward biased. From T1 to T2 the input signal is passed to the output. The diode remains forward biased until the negative alternation has decreased to −5 volts at T2. At T2 the cathode of the diode becomes more positive than the anode, and the diode is again reverse biased and remains so until T3.

Figure 4-5A Series-positive limiter with negative bias Figure 4-5B.— Series-positive limiter with negative bias

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4-9 UNCLASSIFIED 4.1.1.2 Series-Negative Limiter In view (A) of figure 4-6, the SERIES-NEGATIVE LIMITER limits the negative portion of the waveform, as shown in view (B). Let's consider the input signal and determine how the output is produced. During T0 to T1 (view (B)), the anode is more positive than the cathode and the diode conducts. Current flows up through the resistor and the diode, and a positive voltage is developed at the output. The voltage across the resistor is essentially the same as the voltage applied to the circuit.

Figure 4-6A Series-negative limiter Figure 4-6B.— Series-negative limiter

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4-10 UNCLASSIFIED During T1 to T2 the anode is negative with respect to the cathode and the diode does not conduct. This portion of the output is limited because no current flows through the resistor.

As you can see, the only difference between series-positive and series-negative limiters is that the diode is reversed in the negative limiters.

SERIES-NEGATIVE LIMITER WITH BIAS.—View (A) of figure 4 -7 shows a series-negative limiter with negative bias. The diode is forward biased and conducts with no input signal. In view (B) it will continue to conduct as the input signal swings first positive and then negative (but only to −5 volts) from T0 through T1. At T1 the input becomes negative with respect to the −5 volt battery bias. The diode becomes reverse biased and is cutoff until T2 when the anode again becomes positive with respect to the battery voltage (−5 volts) on the cathode. No voltage is developed in the output by R1 (no current flow) and the output is held at −5 volts from T1 to T2. With negative bias applied to a series-negative limiter, only a portion of the negative signal is limited.

Figure 4-7A Series-negative limiter with negative bias Figure 4-7B.— Series-negative limiter with negative bias

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4-11 UNCLASSIFIED Now let's look at a series-negative limiter with positive bias, as shown in figure 4-8, view (A). Here we will remove all of the negative alternation and part of the positive alternation of the input signal. We have given a full explanation of the series-positive limiter, series-positive limiter with bias, series-negative limiter, and series-negative limiter with negative bias; therefore, you should have little difficulty understanding what is happening in the circuit in the figure.

Figure 4-8A Series-negative limiter with positive bins Figure 4-8B.— Series-negative limiter with positive bins

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4-12 UNCLASSIFIED The series-negative limiter with positive bias is different in only one aspect from the series-positive limiter with bias (figure 4-5) discussed earlier. The difference is that the diode is reversed and the output is of the opposite polarity.

Q1. Which portion of a sine-wave input is retained in the output of a series-positive limiter? Q2. Which portion of a sine-wave input is retained in the output of a series-negative limiter? Q3. How can a series-positive limiter be modified to limit unwanted negative portions of the input signal? 4.1.2 Parallel Limiters A PARALLEL-LIMITER circuit uses the same diode theory and voltage divider action as series limiters. A resistor and diode are connected in series with the input signal and the output signal is developed across the diode. The output is in parallel with the diode, hence the circuit name, parallel limiter. The parallel limiter can limit either the positive or negative alternation of the input signal.

Recall that in the series limiter the output was developed while the diode was conducting. In the parallel limiter the output will develop when the diode is cut off. You should not try to memorize the outputs of these circuits; rather, you should study their actions and be able to figure them out.

4.1.2.1 Parallel-Positive Limiter The schematic diagram shown in figure 4-9, view (A), is a PARALLEL-POSITIVE LIMITER. The diode is in parallel with the output and only the positive half cycle of the input is limited. When the positive alternation of the input signal is applied to the circuit (T0 to T1), the diode is forward biased and conducts. This action may be seen in view (B). As current flows up through the diode and the resistor, a voltage is dropped across each. Since R1 is much larger than the forward resistance of D1, most of the input signal is developed across R1. This leaves only a very small voltage across the diode (output). The positive alternation of the input signal has been limited.

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From T1 to T2 the diode is reverse biased and acts as an extremely high resistance. The negative alternation of the input signal appears across the diode at approximately the same amplitude as the input. The negative alternation of the input is not limited.

As with the series limiter, the parallel limiter should provide maximum output voltage for the unlimited part of the signal. The reverse-bias resistance of the diode must be very large compared to the series resistor. To determine the output amplitude, use the following formula:

Figure 4-9A Parallel-positive limiter Figure 4-9B.— Parallel-positive limiter

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PARALLEL-POSITIVE LIMITER WITH BIAS.—Figure 4- 10, view (A), shows the schematic diagram of a PARALLEL-POSITIVE LIMITER WITH NEGATIVE BIAS. The diode is forward biased and conducts without an input signal. D1 is essentially a short circuit. The voltage at the output terminals is -4 volts.

Figure 4-10A Parallel limiter with negative bias

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As the positive alternation of the input signal is applied to the circuit, the diode remains forward biased and limits the entire positive alternation, as shown in view (B). As the signal goes in a negative direction Oust before T1), the diode remains forward biased (limiting is still present) until the input signal exceeds −4 volts (T1). D1 becomes reverse biased as the anode becomes more negative than the cathode. While the input signal is more negative than the −4 volts of the bias battery (T1 to T2), the diode is reverse biased and remains cut off. The output follows the input signal from T1 to T2. At all other times during that cycle, the diode is forward biased and limiting occurs. This circuit is called a parallel-positive limiter with negative bias because the positive output is limited and the bias in the circuit is negative with reference to ground. Limiting takes place at all points more positive than −4 volts.

The circuit shown in figure 4-11, view (A), is a PARALLEL-POSITIVE LIMITER WITH POSITIVE BIAS. The positive terminal of the battery is connected to the cathode of the diode. This causes the diode to be reverse biased at all times except when the input signal is more positive than the bias voltage (T1 to T2), as shown in view (B).

Figure 4-10B.— Parallel limiter with negative bias Figure 4-11A Parallel-positive Limiter with positive bias

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As the positive alternation of the input signal is applied (T0), the output voltage follows the input signal. From T1 to T2 the input signal is more positive than + 4 volts. The diode is forward biased and conducts. At this time the output voltage equals the bias voltage and limiting takes place. From T2 to T4 of the input signal, the diode is reverse biased and does not conduct. The output signal follows the input signal and no limiting takes place.

This circuit is called a parallel-positive limiter with positive bias because limiting takes place in the positive alternation and positive bias is used on the diode.

4.1.2.2 Parallel-Negative Limiter A PARALLEL-NEGATIVE LIMITER is shown in view (A) of figure 4-12. Notice the similarity of the parallel-negative limiter and the parallel-positive limiter shown in view (A) of figure 4-9. From T0 to T1 of the input signal, the diode is reverse biased and does not conduct, as shown in view (B) of figure 4-12. The output signal follows the input signal and the positive alternation is not limited.

Figure 4-11B.—Parallel- positive Limiter with positive bias

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During the negative alternation of the input signal (T1 to T2), the diode is forward biased and conducts. The relatively low forward bias of D1 develops a very small voltage and, therefore, limits the output to nearly 0 volts. A voltage is developed across the resistor as current flows through the resistor and diode.

Figure 4-12A Parallel-negative limiter Figure 4-12B.— Parallel-negative limiter

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4-18 UNCLASSIFIED PARALLEL-NEGATIVE LIMITER WITH BIAS.—The circuit shown in figure 4- 13, view (A), is a parallel-negative limiter with negative bias. With no input, the battery maintains D1 in a reverse-bias condition. D1 cannot conduct until its cathode is more negative than its anode. D1 acts as an open until the input signal dips below −4 volts at T2 in view (B). At T2 the input signal becomes negative enough to forward bias the diode, D1 conducts and acts like a short, and the output is limited to the −4 volts from the battery from T2 to T3. Between T3 and T4 the diode is again reverse biased. The output signal follows the input signal and no limiting occurs.

Figure 4-13A Parallel-negative limiter with negative bias Figure 4-13B.— Parallel-negative limiter with negative bias

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4-19 UNCLASSIFIED Figure 4-14, view (A), shows a parallel-negative limiter with positive bias. The operation is similar to those circuits already explained. Limiting occurs when the diode conducts. No limiting occurs when the diode is reverse biased. In this circuit, the bias battery provides forward bias to the diode without an input signal. The output is at +4 volts, except where the input goes above +4 volts (T1 to T2), as shown in view (B). The parts of the signal more negative than +4 volts are limited.

Figure 4-14A Parallel-negative limiter with positive bias Figure 4-14B.— Parallel-negative limiter with positive bias

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4-21 UNCLASSIFIED Q4. What component is in parallel with the output in a parallel limiter? Q5. What is the condition of the diode in a series limiter when an output is developed? In a parallel limiter? 4.1.3 Dual-Diode Limiter The last type of limiter to be discussed in this chapter is the DUAL-DIODE LIMITER, shown in figure 4-15, view (A). This limiter combines a parallel-negative limiter with negative bias (D1 and B1) and a parallel-positive limiter with positive bias (D2 and B2). Parts of both the positive and negative alternations are removed in this circuit. Each battery aids the reverse bias of the diode in its circuit; the circuit has no current flow with no input signal. When the input signal is below the value of the biasing batteries, both D1 and D2 are reverse biased. With D1 and D2 reverse biased, the output follows the input. When the input signal becomes more positive than +20 volts (view (B)), D2 conducts and limits the output to +20 volts. When the input signal becomes more negative than −20 volts, D1 conducts and limits the output to this, value. When neither diode conducts, the output follows the input waveform.

Figure 4-15A Dual-diode limiter

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4.1.4 Clampers Certain applications in electronics require that the upper or lower extremity of a wave be fixed at a specific value. In such applications, a CLAMPING (or CLAMPER) circuit is used. A clamping circuit clamps or restrains either the upper or lower extremity of a waveform to a fixed dc potential. This circuit is also known as a DIRECT-CURRENT RESTORER or a BASE-LINE STABILIZER. Such circuits are used in test equipment, radar systems, electronic countermeasure systems, and sonar systems. Depending upon the equipment, you could find negative or positive clampers with or without bias. Figure 4-16, views (A) through (E), illustrates some examples of waveforms created by clampers. However, before we discuss clampers, we will review some relevant points about series RC circuits.

Figure 4-15B.—Dual -diode limiter Figure 4-16A Clamping waveforms. WITHOUT CLAMPING

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Figure 4-16B.— Clamping waveforms. WITH CLAMPING, LOWER EXTREMITY OF WAVE IS HELD AT 0V Figure 4-16C.— Clamping waveforms. WITH CLAMPING, LOWER EXTREMITY OF WAVE IS HELD AT +100 V. Figure 4-16D.— Clamping waveforms. WITH CLAMPING, UPPER EXTREMITY OF

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4.2 SERIES RC CIRCUITS Series RC circuits are widely used for coupling signals from one stage to another. If the time constant of the coupling circuit is comparatively long, the shape of the output waveform will be almost identical to that of the input. However, the output dc reference level may be different from that of the input. Figure 4-17, view (A), shows a typical RC coupling circuit in which the output reference level has been changed to 0 volts. In this circuit, the values of R1 and C1 are chosen so that the capacitor will charge (during T0 to T1) to 20 percent of the applied voltage, as shown in view (B). With this in mind, let's consider the operation of the circuit.

Figure 4-16E.— Clamping waveforms. WITH CLAMPING, UPPER EXTREMITY OF

Figure 4-17A RC coupling

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At T0 the input voltage is −50 volts and the capacitor begins charging. At the first instant the voltage across C is 0 and the voltage across R is −50 volts. As C charges, its voltage increases. The voltage across R, which is the output voltage, begins to drop as the voltage across C increases. At T1 the capacitor has charged to 20 percent of the −50 volts input, or −10 volts. Because the input voltage is now 0 volts, the capacitor must discharge. It discharges through the low impedance of the signal source and through R, developing +10 volts across R at the first instant. C discharges 20 percent of the original 10-volt charge from T1 to T2. Thus, C discharges to +8 volts and the output voltage also drops to 8 volts.

At T2 the input signal becomes −50 volts again. This −50 volts is in series opposition to the 8-volt charge on the capacitor. Thus, the voltage across R totals −42 volts (−50 plus +8 volts). Notice that this value of voltage (−42 volts) is smaller in amplitude than the amplitude of the output voltage which occurred at TO (−50 volts). Capacitor C now charges from +8 to +16 volts. If we were to continue to follow the operation of the circuit, we would find that the output wave shape would become exactly distributed around the 0-volt reference point. At that time the circuit operation would have reached a stable operating point. Note that the output wave shape has the same amplitude and approximately the same shape as the input wave shape, but now "rides" equally above and below 0 volts. Clampers use this RC time so that the input and output waveforms will be almost identical, as shown from T11 to T12.

Figure 4-17B.— RC coupling

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4-26 UNCLASSIFIED 4.2.1 Positive-Diode Clampers Figure 4-18, view (A), illustrates the circuit of a positive-diode clamper. Resistor R1 provides a discharge path for C1. This resistance is large in value so that the discharge time of C1 will be long compared to the input pulse width. The diode provides a fast charge path for C1. After C1 becomes charged it acts as a voltage source. The input wave shape shown in view (B) is a square wave and varies between +25 volts and −25 volts. Compare each portion of the input wave shape with the corresponding output wave shape. Keep Kirchhoff's law in mind: The algebraic sum of the voltage drops around a closed loop is 0 at any instant.

Figure 4-18A Positive damper and waveform

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At T0 the −25 volt input signal appears across R1 and D1 (the capacitor is a short at the first instant). The initial voltage across R1 and D1 causes a voltage spike in the output. Because the charge time of C1 through D1 is almost instantaneous, the duration of the pulse is so short that it has only a negligible effect on the output. The −25 volts across D1 makes the cathode negative with respect to the anode and the diode conducts heavily. C1 quickly charges through the small resistance of D1. As the voltage across C1 increases, the output voltage decreases at the same rate. The voltage across C1 reaches -25 volts and the output is at 0 volts.

At T1 the +25 volts already across the capacitor and the +25 volts from the input signal are in series and aid each other (SERIES AIDING). Thus, +50 volts appears across R1 and D1. At this time, the cathode of D1 is positive with respect to the anode, and the diode does not conduct. From T1 to T2, C1 discharges to approximately +23 volts (because of the large values of R and C) and the output voltage drops from +50 volts to +48 volts.

Figure 4-18B.— Positive damper and waveform

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4-28 UNCLASSIFIED At T2 the input signal changes from +25 volts to −25 volts. The input is now SERIES OPPOSING with the +23 volts across C1. This leaves an output voltage of −2 volts (−25 plus +23 volts). The cathode of D1 is negative with respect to the anode and D1 conducts. From T2 to T3, C1 quickly charges through D1 from +23 volts to +25 volts; the output voltage changes from −2 volts to 0 volts.

At T3 the input signal and capacitor voltage are again series aiding. Thus, the output voltage felt across R1 and D1 is again +50 volts. During T3 and T4, C1 discharges 2 volts through R1. Notice that circuit operation from T3 to T4 is the same as it was from T1 to T2. The circuit operation for each square-wave cycle repeats the operation which occurred from T2 to T4.

Compare the input wave shape of figure 4-18, view (B), with the output wave shape. Note the following important points: (1) The peak-to-peak amplitude of the input wave shape has not been changed by the clamper circuit; (2) the shape of the output wave shape has not been significantly changed from that of the input by the action of the clamper circuit; and (3) the output wave shape is now all above 0 volts whereas the input wave shape is both above and below 0 volts. Thus, the lower part of the input wave shape has been clamped to a dc potential of 0 volts in the output. This circuit is referred to as a positive clamper since all of the output wave shape is above 0 volts and the bottom is clamped at 0 volts.

The positive clamper circuit is self-adjusting. This means that the bottom of the output waveform remains clamped at 0 volts during changes in input signal amplitude. Also, the output wave shape retains the form and peak-to-peak amplitude (50 volts in this case) of the input wave shape. When the input amplitude becomes greater, the charge of the capacitor becomes greater and the output amplitude becomes larger. When the input amplitude decreases, the capacitor does not charge as high as before and clamping occurs at a lower output voltage. The capacitor charge, therefore, changes with signal strength.

The size of R1 and C1 has a direct effect upon the operation of the clamper. Because of the small resistance of the diode, the capacitor charge time is short. If either R1 or C1 is made smaller, the capacitor discharges faster (TC = R C).

The ability of a smaller value capacitor to quickly discharge to a lower voltage is an advantage when the amplitude of the input wave shape is suddenly reduced. However, for normal clamper operation, quick discharge time is a disadvantage. This is because one objective of clamping is to keep the output wave shape the same as the input wave shape. If the small capacitor allows a relatively large amount of the voltage to discharge with each cycle, then distortion occurs in the output wave shape. A larger portion of the wave shape then appears on the wrong side of the reference line.

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4-29 UNCLASSIFIED Increasing the value of the resistor increases the discharge time (again, TC = R C). This increased value causes the capacitor to discharge more slowly and produces an output wave shape which is a better reproduction of the input wave shape. A disadvantage of increasing the resistance value is that the larger resistance increases the discharge time of the capacitor and slows the self-adjustment rate of the circuit, particularly in case a sudden decrease in input amplitude should occur. The larger resistance has no effect on self-adjustment with a sudden rise in input amplitude. This is because the capacitor charges through the small resistance of the conducting diode.

Circuits often incorporate a compromise between a short RC time constant (for self- adjustment purposes) and a long RC time constant for less distortion. A point to observe is that the reverse resistance of the diode sometimes replaces the, physical resistor in the discharge path of the capacitor.

4.2.1.1 Positive-Diode Clamper with Bias Biased clamping circuits operate in exactly the same manner as unbiased clampers, with one exception. That exception is the addition of a dc bias voltage in series with the diode and resistor. The size and polarity of this bias voltage determines the output clamping reference.

View (A) of figure 4-19 illustrates the circuit of a positive clamper with positive bias. It can be identified as a positive clamper because the cathode of the diode is connected to the capacitor. Positive bias can be observed by noting that the negative side of the battery is connected to ground. The purposes and actions of the capacitor, resistor, and diode are the same as in the unbiased clamper circuit just discussed.

Figure 4-19A Positive clamper with positive bias

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With no input, D1 is forward biased and the +10 V battery is the output. C1 will charge to +10 V and hold this charge until the first pulse is applied. The battery establishes the dc reference level at +10 volts. The input wave shape at the top of view (B) is a square wave which alternates between +25 and −25 volts. The output wave shape is shown at the bottom half of view (B).

Here, as with previous circuits, let's apply Kirchhoff's voltage law to determine circuit operation. With no input signal, the output is just the +10 volts supplied by the battery.

At time T0 the −25 volt signal applied to the circuit is instantly felt across R1 and D1. The −25 volt input signal forward biases D1, and C1 quickly charges to 35 volts. This leaves +10 volts across the output terminals for much of the period from T0 to T1. The polarity of the charged capacitor is, from the left to the right, minus to plus.

Figure 4-19B.—Positive clamper with positive bias

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4-31 UNCLASSIFIED At T1 the 35 volts across the capacitor is series aiding with the +25 volt input signal. At this point (T1) the output voltage becomes +60 volts; the voltage across R1 and D1 is +50 volts, and the battery is +10 volts. The cathode of D1 is positive with respect to the anode and the diode does not conduct. From T1 to T2, C1 discharges only slightly through the large resistance of R1. Assume that, because of the size of R1 and C1, the capacitor discharges just 2 volts (from +35 volts to +33 volts) during this period. Thus, the output voltage drops from +60 volts to +58 volts.

At T2 the −25 volt input signal and the +33 volts across C1 are series opposing. This makes the voltage across the output terminals +8 volts. The cathode of the diode is 2 volts negative with respect to its anode and D1 conducts. Again, since the forward-biased diode is essentially a short, C1 quickly charges from +33 volts to +35 volts. During most of the time from T2 to T3, then, we find the output voltage is +10 volts.

At T3 the +25 volts of the input signal is series aiding with the +35 volts across C1. Again the output voltage is +60 volts. Observe that at T3 the conditions in the circuit are the same as they were at T1. Therefore, the circuit operation from T3 to T4 is the same as it was from T1 to T2. Circuit operation continues as a duplication of the operations which occurred from T1 to T3.

By comparing the input and output wave shapes, you should note the following: (1) The peak-to peak amplitude of the input wave shape has not been changed in the output (for all practical purposes) by the action of the clamper circuit; (2) the shape of the input wave has not been changed; (3) the output wave shape is now clamped above +10 volts. Remember that this clamping level (+10 volts) is determined by the bias battery.

4.2.1.2 Positive-Diode Clamper with Negative Bias View (A) of figure 4-20 is a positive clamper with negative bias. Observe that with no input signal, the capacitor charges through R1 to the bias battery voltage; the output voltage equals −10 volts. The circuit has negative bias because the positive side of the battery is grounded. The output waveform is shown in view (B). Study the figure and waveforms carefully and note the following important points. Once again the peak-to- peak amplitude and shape of the output wave are, for all practical purposes, the same as the input wave. The lower extremity of the output wave is clamped to −10 volts, the value of the battery. Let's look at the circuit operation. The capacitor is initially charged to −10 volts with no input signal, and diode D1 does not conduct.

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The −25 volt input signal provides forward bias for D1. The capacitor charges to +15 volts and retains most of its charge because its discharge through R1 is negligible. The +25 volt input signal is series aiding the capacitor voltage and develops +40 volts between the output terminals. When the input voltage is −25 volts, D1 conducts and the output voltage is −10 volts (−25 volts plus +15 volts). In this way the output reference is clamped at −10 volts. Changing the size of the battery changes the clamping reference level to the new voltage.

Figure 4-20A Positive clamper with negative bias Figure 4-20B.— Positive clamper with negative bias

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4-33 UNCLASSIFIED 4.2.2 Negative-Diode Clampers Figure 4-21, view (A), illustrates the circuit of a negative-diode clamper. Compare this with the positive-diode clamper in view (A) of figure 4-18. Note that the diode is reversed with reference to ground. Like the positive clamper, resistor R1 provides a discharge path for C1; the resistance must be a large value for C1 to have a long discharge time. The low resistance of the diode provides a fast charge path for C1. Once C1 becomes charged, it acts as a source of voltage which will help determine the maximum and minimum voltage levels of the output wave shape. The input wave shape shown in view (B) is a square wave which varies between +25 and 25 volts. The output wave shapes are shown in the bottom half of view (B). You will find that the operation of the negative clamper is similar to that of the positive clamper, except for the reversal of polarities.

Figure 4-21A Negative clamper and waveform Figure 4-21B.— Negative clamper and waveform

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4-34 UNCLASSIFIED At T0 the +25 volt input signal applied to the circuit appears across R1 and D1. This makes the anode of D1 positive with respect to the cathode and it conducts heavily. Diode resistance is very small causing C1 to charge quickly. As the voltage across C1 increases, the output voltage decreases. The voltage across C1 reaches 25 volts quickly; during most of T0 to T1, the output voltage is 0.

At T1 the voltage across the capacitor and the input voltage are series aiding and result in −50 volts appearing at the output. At this time the diode is reverse biased and does not conduct. Because of the size of R and C, the capacitor discharges only 2 volts to approximately 23 volts from T1 to T2. Using Kirchhoff's voltage law to determine voltage in the circuit, we find that the output voltage decreases from −50 to −48 volts.

At T2 the +25 volt input signal and the 23 volts across C1 are series opposing. The output voltage is +2 volts. The anode of D1 is positive with respect to the cathode and D1 will conduct. From T2 to T3, C1 charges quickly from 23 to 25 volts through D1. At the same time, the output voltage falls from +2 to 0 volts.

At T3 the input and capacitor voltages are series aiding and the total output voltage is −50 volts. From T3 to T4, D1 is reverse biased and C discharges through R. The circuit operation is now the same as it was from T1 to T2. The circuit operation for the following square-wave cycles duplicates the operation which occurred from T1 to T3.

As was the case with the positive clamper, the amplitude and wave, shape of the output is almost identical to that of the input. However, note that the upper extremity of the output wave shape is clamped to 0 volts; that is, the output wave shape, for all practical purposes, lies entirely below the 0-volt reference level.

4.2.2.1 Negative-Diode Clamper with Negative Bias View (A) of figure 4-22 is the circuit of a negative clamper with negative bias. Again, with no input signal the capacitor charges to the battery voltage and the output is negative because the positive side of the battery is ground. The bottom of view (B) shows the output of the circuit. Study the figure carefully, and note the following important points. The peak-to-peak amplitude and shape of the output wave, for all practical purposes, are the same as that of the input wave. The output wave is clamped to −10 volts which is the value of the battery. Since this is a negative clamper, the upper extremity of the waveform touches the −10 volt reference line (and the rest of it lies below this voltage level).

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Figure 4-22A Negative damper with negative bias Figure 4-22B.— Negative damper with negative bias

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4-36 UNCLASSIFIED Let's review the important points of circuit operation. The capacitor is initially charged to −10 volts with no input signal. Applying Kirchhoff's law we find that the +25 volt input signal and the 10-volt battery are series opposing. This series opposing forward biases D1 and the capacitor charges to −35 volts. The output voltage is equal to the sum of the capacitor voltage and the input voltage. Thus, the output voltage is −10 volts and the wave shape is clamped to −10 volts. With a −25 volt input, the charge maintained across C1 and the input are series aiding and provide a −60 volt output. C1 will discharge just before the next cycle begins and the input becomes positive. The +25 volt input signal and the approximately −23 volt charge remaining on C1 will forward bias D1 and the output will be clamped to the battery voltage. C1 will quickly charge to the input signal level. Thus, the output voltage varies between −10 and −60 volts and the wave shape is clamped to −10 volts.

4.2.2.2 Negative Clamper with Positive Bias View (A) of figure 4-23 illustrates the circuit of a negative clamper with positive bias. With no input signal the capacitor charges to the battery voltage and the output is positive because the negative side of the battery is grounded. The output is illustrated in the bottom half of view (B). Study the figure carefully and note the following important points. The peak-to-peak amplitude and shape of the output waveform, for all practical purposes, are the same as that of the input. The output wave is clamped to +10 volts, the value of the battery. Since this is a negative clamper (cathode to ground), the top of the output wave touches the +10 volt reference line.

Figure 4-23A Negative clamper with positive bias

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Let's go over a summary of the circuit operation. With no input signal the capacitor charges to 10 volts. The +25 volt input signal forward biases D1. With the 10-volt battery and the input in series, the capacitor charges to −15 volts. The capacitor remains charged, for all practical purposes, since its discharge through R1 (very large) is almost negligible. The output voltage is equal to the algebraic sum of the capacitor voltage and the input voltage. The +25 volt input signal added to the −15 volt capacitor charge provides a +10 volt output. With a −25 volt input at T1, D1 is reverse-biased and the charge across C 1 adds to the input voltage to provide a −40 volt output. From T1 to T2, the capacitor loses only a small portion of its charge. At T2 the input signal is +25 volts and the input returns to +10 volts. The wave shape is negatively clamped to +10 volts by the battery.

We can say, then, that positive clamping sets the wave shape above (negative peak on) the reference level, and negative clamping places the wave shape below (positive peak on) the reference level.

Figure 4-23B.—Negative clamper with positive bias

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4-38 UNCLASSIFIED Q6. What is the relative length of the time constant for the diode-capacitor combination in a damper (long or short)? Q7. What is the relative length of the discharge time constant with respect to the charge time constant of a damper (long or short)? Q8. A positive damper clamps which extremity of the output signal to 0 volts? Q9. To which polarity does a positive damper with positive bins clamp the most negative extremity of the output waveform (positive or negative)? Q10. What type damper (with bias) clamps the most negative extremity of the output waveform to a negative potential? Q11. A negative damper damps which extremity of the output waveshape to 0 volts? Q12. A negative damper with negative bias clamps the most positive extremity of the output wave shape to what polarity (positive or negative)? Q13. What type of bias (positive or negative) is added to a negative damper for the most positive extremity of the wave shape to be clamped above 0 volts? Q14. What would be the output of a negative clamper with a bias potential of −5 volts and an input voltage swing from +50 to −50 volts?

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4-39 UNCLASSIFIED 4.2.3 Common-Base Transistor Clamper The common-base transistor clamper is similar to the dual diode limiter in figure 4-15, except for the addition of a transistor. In the previous clampers, we have clamped the output signal to a reference. In the transistor common-base clamper, we want to clamp the amplitude of the input to no more than nor less than certain values in the output. Also, we do not want phase inversion in the output. View (A) of figure 4-24 shows such a circuit. The transistor does not amplify the input and the output is not inverted. However, the two diode circuits serve to clamp the output between −2 volts and −8 volts, no matter what the varying input positive and negative extremes.

Figure 4-24A Common-base configuration clamper Figure 4-24B.—Common -base configuration clamper

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4-40 UNCLASSIFIED Look at view (B) as we continue. The input signal is a square-wave pulse type signal that varies in amplitude. Without an input signal, Q1 conducts and provides current through R1. This develops the output (collector to ground) potential which is assumed to be approximately −5 volts (VCC −ER1) for this discussion.

From T0 to T1 the output follows the input because of the increasing emitter-base forward bias. However, at T1 the collector voltage reaches −2 volts and D2 is forward biased. D2 conducts and limits the output to −2 volts (the value of B3). D2 conducts until T2 when the input decreases below −2 volts. At this time, D2 cuts off and the output again follows the input because of the decreasing forward bias on Q1. At T3 the input reaches −8 volts and forward biases D1. D1 conducts and any further increase (beyond −8 volts) of the input has no effect on the output. When the input returns to a value more positive than −8 volts, D1 cuts off and the output again follows the input. This circuit action is the same for all inputs. The output remains the same as the input except that both positive and negative extremes are clamped at −2 and −8 volts, respectively.

4.3 SHAPING CIRCUITS Timing circuits and circuits which require a particular shape or "spike" of voltage, may use SHAPING circuits. Shaping circuits can be used to cause wave shapes, such as square waves, sawtooth waves, and trapezoidal waves, to change their shape. Shaping circuits may be either series RC or series RL circuits. The time constant is controlled in respect to the duration of the applied waveform. Notice that the wave shapes mentioned did not include the sine wave. These RC or RL shaping circuits do not change the shape of a pure sine wave.

The series RC and RL circuits electrically perform the mathematical operations of INTEGRATION and DIFFERENTIATION. Therefore, the circuits used to perform these operations are called INTEGRATORS and DIFFERENTIATORS. These names are applied to these circuits even though they do not always completely perform the operations of mathematical integration and differentiation.

4.4 COMPOSITION OF NONSINUSOIDAL WAVES Pure sine waves are basic wave shapes from which other wave shapes can be constructed. Any waveform that is not a pure sine wave consists of two or more sine waves. Adding the correct frequencies at the proper phase and amplitude will form square waves, sawtooth waves, and other nonsinusoidal waveforms.

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4-41 UNCLASSIFIED A waveform other than a sine wave is called a COMPLEX WAVE. You will see that a complex wave consists of a fundamental frequency plus one or more HARMONIC frequencies. The shape of a nonsinusoidal waveform is dependent upon the type of harmonics present as part of the waveform, their relative amplitudes, and their relative phase relationships. In general, the steeper the sides of a waveform, that is, the more rapid its rise and fall, the more harmonics it contains.

The sine wave which has the lowest frequency in the complex periodic wave is referred to as the FUNDAMENTAL FREQUENCY. The type and number of harmonics included in the waveform are dependent upon the shape of the waveform. Harmonics have two classifications — EVEN numbered and ODD numbered. Harmonics are always a whole number of times higher than the fundamental frequency and are designated by an integer (whole number). For example, the frequency twice as high as the fundamental frequency is the SECOND HARMONIC (or the first even harmonic).

View (A) of figure 4-25 compares a square wave with sine waves. Sine wave K is the same frequency as the square wave (its fundamental frequency). If another sine wave (L) of smaller amplitude but three times the frequency (referred to as the third harmonic) is added to sine wave K, curve M is produced. The addition of these two waveforms is accomplished by adding the instantaneous values of both sine waves algebraically. Curve M is called the resultant. Notice that curve M begins to assume the shape of a square wave. Curve M is shown again in view (B).

Figure 4-25 Harmonic composition of a square wave

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4-42 UNCLASSIFIED As shown in view (B), when the fifth harmonic (curve N with its decreased amplitude) is added, the sides of the new resultant (curve P) are steeper than before. In view (C), the addition of the seventh harmonic (curve Q), which is of even smaller amplitude, makes the sides of the composite waveform (R) still steeper. The addition of more odd harmonics will bring the composite waveform nearer the shape of the perfect square wave. A perfect square wave is, therefore, composed of an infinite number of odd harmonics. In the composition of square waves, all the odd harmonics cross the reference line in phase with the fundamental.

A sawtooth wave, shown in figure 4-26, is made up of both even and odd harmonics. Notice that each higher harmonic is added in phase as it crosses the 0 reference in view (A), view (B), view (C), and view (D). The resultant, shown in view (D), closely resembles a sawtooth waveform.

Figure 4-26A Composition of a sawtooth wave

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Figure 4-26B.— Composition of a sawtooth wave Figure 4-26C.— Composition of a sawtooth wave

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Figure 4-27 shows the composition of a peaked wave. Notice how the addition of each odd harmonic makes the peak of the resultant higher and the sides steeper. The phase relationship between the harmonics of the peaked wave is different from the phase relationship of the harmonics in the composition of the square wave. In the composition of the square wave, all the odd harmonics cross the reference line in phase with the fundamental. In the peaked wave, harmonics such as the third, seventh, and so forth, cross the reference line 180 degrees out of phase with the fundamental; the fifth, ninth, and so forth, cross the reference line in phase with the fundamental.

Figure 4-26D.— Composition of a sawtooth wave

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Q15. What is the harmonic composition of a square wave? Q16. What is the peaked wave composed of? Q17. What is the fundamental difference between the phase relationship of the harmonics of the square wave as compared to the harmonics of a peaked wave?

Figure 4-27 Composition of a peaked wave

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4-46 UNCLASSIFIED 4.4.1 Nonsinusoidal Voltages Applied to an RC Circuit The harmonic content of a square wave must be complete to produce a pure square wave. If the harmonics of the square wave are not of the proper phase and amplitude relationships, the square wave will not be pure. The term PURE, as applied to square waves, means that the waveform must be perfectly square.

Figure 4-28 shows a pure square wave that is applied to a series-resistive circuit. If the values of the two resistors are equal, the voltage developed across each resistor will be equal; that is, from one pure square-wave input, two pure square waves of a lower amplitude will be produced. The value of the resistors does not affect the phase or amplitude relationships of the harmonics contained within the square waves. This is true because the same opposition is offered by the resistors to all the harmonics presented. However, if the same square wave is applied to a series RC circuit, as shown in figure 4- 29, the circuit action is not the same.

Figure 4-28 Square wave applied to a resistive circuit Figure 4-29 Square wave applied to an RC circuit

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4-47 UNCLASSIFIED 4.5 RC INTEGRATORS The RC INTEGRATOR is used as a waveshaping network in communications, radar, and computers. The harmonic content of the square wave is made up of odd multiples of the fundamental frequency. Therefore SIGNIFICANT HARMONICS (those that have an effect on the circuit) as high as 50 or 60 times the fundamental frequency will be present in the wave. The capacitor will offer a reactance (XC) of a different magnitude to each of the harmonics.

This means that the voltage drop across the capacitor for each harmonic frequency present will not be the same. To low frequencies, the capacitor will offer a large opposition, providing a large voltage drop across the capacitor. To high frequencies, the reactance of the capacitor will be extremely small, causing a small voltage drop across the capacitor. This is no different than was the case for low- and high pass filters (discriminators) presented in chapter 1. If the voltage component of the harmonic is not developed across the reactance of the capacitor, it will be developed across the resistor, if we observe Kirchhoff's voltage law. The harmonic amplitude and phase relationship across the capacitor is not the same as that of the original frequency input; therefore, a perfect square wave will not be produced across the capacitor. You should remember that the reactance offered to each harmonic frequency will cause a change in both the amplitude and phase of each of the individual harmonic frequencies with respect to the current reference. The amount of phase and amplitude change taking place across the capacitor depends on the X C of the capacitor. The value of the resistance offered by the resistor must also be considered here; it is part of the ratio of the voltage development across the network.

The circuit in figure 4-30 will help show the relationships of R and X C more clearly. The square wave applied to the circuit is 100 volts peak at a frequency of 1 kilohertz. The odd harmonics will be 3 kilohertz, 5 kilohertz, 7 kilohertz, etc. Table 4-1 shows the values of XC and R offered to several harmonics and indicates the approximate value of the cutoff frequency (XC = R). The table clearly shows that the cutoff frequency lies between the fifth and seventh harmonics. Between these two values, the capacitive reactance will equal the resistance. Therefore, for all harmonic frequencies above the fifth, the majority of the output voltage will not be developed across the output capacitor. Rather, most of the output will be developed across R. The absence of the higher order harmonics will cause the leading edge of the waveform developed across the capacitor to be rounded. An example of this effect is shown in figure 4-31. If the value of the capacitance is increased, the reactances to each harmonic frequency will be further decreased. This means that even fewer harmonics will be developed across the capacitor.

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Figure 4-30 Partial integration circuit Figure 4-31 Partial integration

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The harmonics not effectively developed across the capacitor must be developed across the resistor to satisfy Kirchhoff's voltage law. Note the pattern of the voltage waveforms across the resistor and capacitor. If the waveforms across both the resistor and the capacitor were added graphically, the resultant would be an exact duplication of the input square wave.

When the capacitance is increased sufficiently, full integration of the input signal takes place in the output across the capacitor. An example of complete integration is shown in figure 4-32 (waveform e C). This effect can be caused by significantly decreasing the value of capacitive reactance. The same effect would take place by increasing the value of the resistance. Integration takes place in an RC circuit when the output is taken across the capacitor.

Table 4-1 Resistive and reactive values

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The amount of integration is dependent upon the values of R and C. The amount of integration may also be dependent upon the time constant of the circuit. The time constant of the circuit should be at least 10 TIMES GREATER than the time duration of the input pulse for integration to occur. The value of 10 is only an approximation. When the time constant of the circuit is 10 or more times the value of the duration of the input pulse, the circuit is said to possess a long time constant. When the time constant is long, the capacitor does not have the ability to charge instantly to the value of the applied voltage. Therefore, the result is the long, sloping, integrated waveform.

Q18. What are the requirements for an integration circuit? Q19. Can a pure sine wave be integrated? Why?

Figure 4-32 Integration

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4-51 UNCLASSIFIED 4.6 RL INTEGRATORS The RL circuit may also be used as an integrating circuit. An integrated waveform may be obtained from the series RL circuit by taking the output across the resistor. The characteristics of the inductor are such that at the first instant of time in which voltage is applied, current flow through the inductor is minimum and the voltage developed across it is maximum. Therefore, the value of the voltage drop across the series resistor at that first instant must be 0 volts because there is no current flow through it. As time passes, current begins to flow through the circuit and voltage develops across the resistor. Since the circuit has a long time constant, the voltage across the resistor does NOT respond to the rapid changes in voltage of the input square wave. Therefore, the conditions for integration in an RL circuit are a long time constant with the output taken across the resistor. These conditions are shown in figure 4-33.

Q20. What characteristic of an RL circuit allows it to act as an integrator?

Figure 4-33 RL integrator waveform

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4-52 UNCLASSIFIED 4.7 INTEGRATOR WAVEFORM ANALYSIS If either an RC or RL circuit has a time constant 10 times greater than the duration of the input pulse, the circuits are capable of integration. Let's compute and graph the actual waveform that would result from a long time constant (10 times the pulse duration), a short time constant (1/10 of the pulse duration), and a medium time constant (that time constant between the long and the short). To accurately plot values for the capacitor output voltage, we will use the Universal Time Constant Chart shown in figure 4-34.

Figure 4-34 Universal Time Constant Chart

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4-53 UNCLASSIFIED You already know that capacitor charge follows the shape of the curve shown in figure 4- 34. This curve may be used to determine the amount of voltage across either component in the series RC circuit. As long as the time constant or a fractional part of the time constant is known, the voltage across either component may be determined.

4.7.1 Short Time-Constant Integrator In figure 4-35, a 100-microsecond pulse at an amplitude of 100 volts is applied to the circuit. The circuit is composed of the, 0.01μF capacitor and the variable resistor, R. The square wave applied is a pure square wave. The resistance of the variable resistor is set at a value of 1,000 ohms. The time constant of the circuit is given by the equation:

Substituting values:

Figure 4-35 RC integrator circuit

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4-54 UNCLASSIFIED Since the time constant of the circuit is 10 microseconds and the pulse duration is 100 microseconds, the time constant is short (1/10 of the pulse duration). The capacitor is charged exponentially through the resistor. In 5 time constants, the capacitor will be, for all practical purposes, completely charged. At the first time constant, the capacitor is charged to 63.2 volts, at the second 86.5 volts, at the third 95 volts, at the fourth 98 volts, and finally at the end of the fifth time constant (50 microseconds), the capacitor is fully charged. This is shown in figure 4-36.

Notice that the leading edge of the square wave taken across the capacitor is rounded. If the time constant were made extremely short, the rounded edge would become square.

4.7.2 Medium Time-Constant Integrator The time constant, in figure 4-36 can be changed by increasing the value of the variable resistor (figure 4-35) to 10,000 ohms. The time constant will then be equal to 100 microseconds.

This time constant is known as a medium time constant. Its value lies between the extreme ranges of the short and long time constants. In this case, its value happens to be exactly equal to the duration of the input pulse, 100 microseconds. The output waveform, after several time constants, is shown in figure 4-37. The long, sloping rise and fall of voltage is caused by the inability of the capacitor to charge and discharge rapidly through the 10,000-ohm series resistance.

Figure 4-36 Square wave applied to a short time-constant integrator

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At the first instant of time, 100 volts is applied to the medium time-constant circuit. In this circuit, 1TC is exactly equal to the duration of the input pulse. After 1TC the capacitor has charged to 63.2 percent of the input voltage (100 volts). Therefore, at the end of 1TC (100 microseconds), the voltage across the capacitor is equal to 63.2 volts. However, as soon as 100 microseconds has elapsed, and the initial charge on the capacitor has risen to 63.2 volts, the input voltage suddenly drops to 0. It remains there for 100 microseconds. The capacitor will now discharge for 100 microseconds. Since the discharge time is 100 microseconds (1TC), the capacitor will discharge 63.2 percent of its total 63.2-volt charge, a value of 23.3 volts. During the next 100 microseconds, the input voltage will increase from 0 to 100 volts instantaneously. The capacitor will again charge for 100 microseconds (1TC). The voltage available for this charge is the difference between the voltage applied and the charge on the capacitor (100 - 23.3 volts), or 76.7 volts. Since the capacitor will only be able to charge for 1TC, it will charge to 63.2 percent of the 76.7 volts, or 48.4 volts. The total charge on the capacitor at the end of 300 microseconds will be 23.3 + 48.4 volts, or 71.7 volts.

Notice that the capacitor voltage at the end of 300 microseconds is greater than the capacitor voltage at the end of 100 microseconds. The voltage at the end of 100 microseconds is 63.2 volts, and the capacitor voltage at the end of 300 microseconds is 71.7 volts, an increase of 8.5 volts.

The output waveform in this graph (e C) is the waveform that will be produced after many cycles of input signal to the integrator. The capacitor will charge and discharge in a step- by-step manner until it finally charges and discharges above and below a 50-volt level. The 50-volt level is controlled by the maximum amplitude of the symmetrical input pulse, the average value of which is 50 volts.

Figure 4-37 Medium time-constant integrator

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4-56 UNCLASSIFIED 4.7.3 Long Time-Constant Integrator If the resistance in the circuit of figure 4-35 is increased to 100,000 ohms, the time constant of the circuit will be 1,000 microseconds. This time constant is 10 times the pulse duration of the input pulse. It is, therefore, a long time-constant circuit.

The shape of the output waveform across the capacitor is shown in figure 4-38. The shape of the output waveform is characterized by a long, sloping rise and fall of capacitor voltage.

At the first instant of time, 100 volts is applied to the long time-constant circuit. The value of charge on the capacitor at the end of the first 100 microseconds of the input signal can be found by using the Universal Time Constant Chart (figure 4-34). Assume that a line is projected up from the point on the base line corresponding to 0.1TC. The line will intersect the curve at a point that is the percentage of voltage across the capacitor at the end of the first 100 microseconds. Since the applied voltage is 100 volts, the charge on the capacitor at the end of the first 100 microseconds will be approximately 9.5 volts. At the end of the first 100 microseconds, the input signal will fall suddenly to 0 and the capacitor will begin to discharge. It will be able to discharge for 100 microseconds. Therefore, the capacitor will discharge 9.5 percent of its accumulated 9.5 volts (.095 × 9.5 = 0.90 volt). The discharge of the 0.90 volt will result in a remaining charge on the capacitor of 8.6 volts. At the end of 200 microseconds, the input signal will again suddenly rise to a value of 100 volts. The capacitor will be able to charge to 9.5 percent of the difference (100 − 8.6 = 91.4 volts). This may also be figured as a value of 8.7 volts plus the initial 8.6 volts. This results in a total charge on the capacitor (at the end of the first 300 microseconds) of 8.7 + 8.6 = 17.3 volts.

Figure 4-38 Square wave applied to a long time-constant integrator

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4-57 UNCLASSIFIED Notice that the capacitor voltage at the end of the first 300 microseconds is greater than the capacitor voltage at the end of the first 100 microseconds. The voltage at the end of the first 100 microseconds is 9.5 volts; the capacitor voltage at the end of the first 300 microseconds is 17.3 volts, an increase of 7.8 volts.

The capacitor charges and discharges in this step-by-step manner until, finally, the capacitor charges and discharges above and below a 50-volt level. The 50-volt level is controlled by the maximum amplitude of the square-wave input pulse, the average value of which is 50 volts.

Q21. What is the numerical difference (in terms of the time constant) between a long and a short time constant circuit? Q22. What would happen to the integrator output if the capacitor were made extremely large (all other factors remaining the same)? 4.8 DIFFERENTIATORS DIFFERENTIATION is the direct opposite of integration. In the RC integrator, the output is taken from the capacitor. In the differentiator, the output is taken across the resistor. Likewise, this means that when the RL circuit is used as a differentiator, the differentiated output is taken across the inductor.

An application of Kirchhoff's law shows the relationship between the waveforms across the resistor and capacitor in a series network. Since the sum of the voltage drops in a closed loop must equal the total applied voltage, the graphical sum of the voltage waveforms in a closed loop must equal the applied waveform. Figure 4-39 shows a differentiator circuit with the output taken across a variable resistor.

Figure 4-39 RC circuit as a differentiator

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4-58 UNCLASSIFIED 4.8.1 Short Time-Constant Differentiator With the variable resistor set at 1,000 ohms and the capacitor value of 0.01 microfarad, the time constant of the circuit is 10 microseconds. Since the input waveform has a duration of 100 microseconds, the circuit is a short time-constant circuit.

At the first instant of time in the short time-constant circuit, the voltage across the capacitor is 0. Current flows through the resistor and causes a maximum voltage to be developed across it. This is shown at the first instant of time in the graph of figure 4-40.

As the capacitor begins accumulating a charge, the voltage developed across the resistor will begin to decrease. At the end of the first time constant, the voltage developed across the resistor will have decreased by a value equal to 63.2 percent of the applied voltage. Since 100 volts is applied, the voltage across the resistor after 1TC will be equal to 36.8 volts. After the second time constant, the voltage across the resistor will be down to 13.5 volts. At the end of the third time constant, e R will be 5 volts and at the end of the fourth time constant, 2 volts. At the end of the fifth time constant, the voltage across the resistor will be very close to 0 volts. Since the time constant is equal to 10 microseconds, it will take a total of 50 microseconds to completely charge the capacitor and stop current flow in the circuit.

Figure 4-40 Square wave applied to a short time-constant differentiator

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4-59 UNCLASSIFIED As shown in figure 4-40 the slope of the charge curve will be very sharp. The voltage across the resistor will remain at 0 volts until the end of 100 microseconds. At that time, the applied voltage suddenly drops to 0, and the capacitor will now discharge through the resistor. At this time, the discharge current will be maximum causing a large discharge voltage to develop across the resistor. This is shown as the negative spike in figure 4-40. Since the current flow from the capacitor, which now acts like a source, is decreasing exponentially, the voltage across the resistor will also decrease. The resistor voltage will decrease exponentially to 0 volts in 5 time constants. All of this discharge action will take a total of 50 microseconds. The discharge curve is also shown in figure 4-40. At the end of 200 microseconds, the action begins again. The output waveform taken across the resistor in this short time-constant circuit is an example of differentiation. With the square wave applied, positive and negative spikes are produced in the output. These spikes approximate the rate of change of the input square wave.

4.8.2 Medium Time-Constant Differentiator The output across the resistor in an RC circuit of a medium time constant is shown in figure 4-41. The value of the variable resistor has been increased to a value of 10,000 ohms. This means that the time constant of the circuit is equal to the duration of the input pulse or 100 microseconds. For clarity, the voltage waveforms developed across both the resistor and the capacitor are shown. As before, the sum of the voltages across the resistor and capacitor must be equal to the applied voltage of 100 volts.

Figure 4-41 Voltage outputs in a medium time-constant differentiator

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4-60 UNCLASSIFIED At the first instant of time, a pulse of 100 volts in amplitude with a duration of 100 microseconds is applied. Since the capacitor cannot respond quickly to the change in voltage, all of the applied voltage is felt across the resistor. Figure 4-41 shows the voltage across the resistor (eR) to be 100 volts and the voltage across the capacitor (eC) to be 0 volts. As time progresses, the capacitor charges. As the capacitor voltage increases, the resistor voltage decreases. Since the time that the capacitor is permitted to charge is 100 microseconds (equal to 1TC in this circuit), the capacitor will charge to 63.2 percent of the applied voltage at the end of 1TC, or 63.2 volts. Because Kirchhoff's law must be followed at all times, the voltage across the resistor must be equal to the difference between the applied voltage and the charge on the capacitor (100 − 63.2 volts), or 36.8 volts.

At the end of the first 100 microseconds, the input voltage suddenly drops to 0 volts. The charge on the capacitor (−63.2 volts) becomes the source and the entire voltage is developed across the resistor for the first instant.

The capacitor discharges during the next 100 microseconds. The voltage across the resistor decreases at the same rate as the capacitor voltage and total voltage is maintained at 0. This exponential decrease in resistor voltage is shown during the second 100 microseconds in figure 4-41. The capacitor will discharge 63.2 percent of its charge to a value of 23.3 volts at the end of the second 100 microseconds. The resistor voltage will rise in the positive direction to a value of −23.3 volts to maintain the total voltage at 0 volts.

At the end of 200 microseconds, the input voltage again rises suddenly to 100 volts. Since the capacitor cannot respond to the 100-volt increase instantaneously, the 100-volt change takes place across the resistor. The voltage across the resistor suddenly rises from −23.3 volts to +76.7 volts. The capacitor will now begin to charge for 100 microseconds. The voltage will decrease across the resistor. This charge and discharge action will continue for many cycles. Finally, the voltage across the capacitor will rise and fall by equal amounts both above and below about a 50-volt level. The resistor voltage will also rise and fall by equal amounts to about a 0-volt level.

4.8.3 Long Time-Constant Differentiator If the time constant for the circuit in figure 4-39 is increased to make it a long time- constant circuit, the differentiator output will appear more like the input. The time constant for the circuit can be changed by either increasing the value of capacitance or resistance. In this circuit, the time constant will be increased by increasing the value of resistance from 10,000 ohms to 100,000 ohms. Increasing the value of resistance will result in a time constant of 1,000 microseconds. The time constant is 10 times the duration of the input pulse. The output of this long time-constant circuit is shown in figure 4-42.

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At the first instant of time, a pulse of 100-volts amplitude with a duration of 100 microseconds is applied. Since the capacitor cannot respond instantaneously to a change in voltage, all of the applied voltage is felt across the resistor. As time progresses, the capacitor will charge and the voltage across the resistor will be reduced. Since the time that the capacitor is permitted to charge is 100 microseconds, the capacitor will charge for only 1/10 of 1TC or to 9.5 percent of the applied voltage. The voltage across the resistor must be equal to the difference between the applied voltage and the charge on the capacitor (100 − 9.5 volts), or 90.5 volts.

At the end of the first 100 microseconds of input, the applied voltage suddenly drops to 0 volts, a change of 100 volts. Since the capacitor is not able to respond to so rapid a voltage change, it becomes the source of 9.5 volts. This causes a −9.5 voltage to be felt across the resistor in the first instant of time. The sum of the voltage across the two components is now 0 volts.

During the next 100 microseconds, the capacitor discharges. The total circuit voltage is maintained at 0 by the voltage across the resistor decreasing at exactly the same rate as the capacitor discharge. This exponential decrease in resistor voltage is shown during the second 100 microseconds of operation. The capacitor will now discharge 9.5 percent of its charge to a value of 8.6 volts. At the end of the second 100 microseconds, the resistor voltage will rise in a positive direction to a value of 8.6 volts to maintain the total circuit voltage at 0 volts.

Figure 4-42 Voltage outputs in a long time-constant differentiator

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4-62 UNCLASSIFIED At the end of 200 microseconds, the input voltage again suddenly rises to 100 volts. Since the capacitor cannot respond to the 100-volt change instantaneously, the 100-volt change takes place across the resistor. This step-by-step action will continue until the circuit stabilizes. After many cycles have passed, the capacitor voltage varies by equal amounts above and below the 50-volt level. The resistor voltage varies by equal amounts both above and below a 0-volt level.

The RC networks which have been discussed in this chapter may also be used as coupling networks. When an RC circuit is used as a coupling circuit, the output is taken from across the resistor. Normally, a long time-constant circuit is used. This, of course, will cause an integrated wave shape across the capacitor if the applied signal is nonsinusoidal. However, in a coupling circuit, the signal across the resistor should closely resemble the input signal and will if the time constant is sufficiently long. By referring to the diagram in figure 4-42, you can see that the voltage across the resistor closely resembles the input signal. Consider what would happen if a pure sine wave were applied to a long time- constant RC circuit (R is much greater than X C). A large percentage of the applied voltage would be developed across the resistor and only a small amount across the capacitor.

Q23. What is the difference between an RC and an RL differentiator in terms of where the output is developed? 4.9 COUNTERS A counting circuit receives uniform pulses representing units to be counted. It provides a voltage that is proportional to the frequency of the units.

With slight modification, the counting circuit can be used with a blocking oscillator to produce trigger pulses which are a submultiple of the frequency of the pulses applied. In this case the circuit acts as a frequency divider.

The pulses applied to the counting circuit must be of the same time duration if accurate frequency division is to be made. Counting circuits are generally preceded by shaping circuits and limiting circuits (both discussed in this chapter) to ensure uniformity of amplitude and pulse width. Under those conditions, the pulse repetition frequency is the only variable and frequency variations may be measured.

Q24. Name a common application of counting circuits.

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4-63 UNCLASSIFIED 4.9.1 Positive Counters The POSITIVE-DIODE COUNTER circuit is used in timing or counting circuits in which the number of input pulses are represented by the output voltage. The output may indicate frequency, count the rpm of a shaft, or register a number of operations. The counter establishes a direct relationship between the input frequency and the average dc output voltage. As the input frequency increases, the output voltage also increases; conversely, as the input frequency decreases, the output voltage decreases. In effect, the positive counter counts the number of positive input pulses by producing an average dc output voltage proportional to the repetition frequency of the input signal. For accurate counting, the pulse repetition frequency must be the only variable parameter in the input signal. Therefore, careful shaping and limiting of the input signal is essential for you to ensure that the pulses are of uniform width and that the amplitude is constant. When properly filtered and smoothed, the dc output voltage of the counter may be used to operate a direct reading indicator.

Solid-state and electron-tube counters operate in manners similar to each other. The basic solid-state (diode) counter circuit is shown in view (A) of figure 4-43. Capacitor C1 is the input coupling capacitor. Resistor R1 is the load resistor across which the output voltage is developed. For the purpose of circuit discussion, assume that the input pulses (shown in view (B)) are of constant amplitude and time duration and that only the pulse repetition frequency changes. At time T0, the positive-going input pulse is applied to C1 and causes the anode of D2 to become positive. D2 conducts and current i c flows through R1 and D2 to charge C1. Current ic, develops an output voltage across R1, shown as eout.

Figure 4-43A Positive-diode counter and waveform

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The initial heavy flow of current produces a large voltage across R1 which tapers off exponentially as C1 charges. The charge on C1 is determined by the time constant of R1 and the conducting resistance of the diode times the capacitance of C1. For ease of explanation, assume that C1 is charged to the peak value before T1.

At T1 the input signal reverses polarity and becomes negative-going. Although the charge on capacitor C1 cannot change instantly, the applied negative voltage is equal to or greater than the charge on C1. This causes the anode of D2 to become negative and conduction ceases. When D2 stops conducting e out is at 0. C1 quickly discharges through D1 since its cathode is now negative with respect to ground. Between T1 and T2 the input pulse is again at the 0-volt level and D2 remains in a non-conducting state. Since the very short time constant provided by the conduction resistance of D1 and C1 is so much less than the long time constant offered by D2 and R1 during the conduction period, C1 is always completely discharged between pulses. Thus, for each input pulse, a precise level of charge is deposited on C1. For each charge of C1 an identical output pulse is produced by the flow of ic through R1. Since this current flow always occurs in the direction indicated by the solid arrow, the dc output voltage is positive.

Figure 4-43B.— Positive-diode counter and waveform

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4-65 UNCLASSIFIED At T2 the input signal again becomes positive and the cycle repeats. The time duration between pulses is the interval represented by the period between T1 and T2 or between T3 and T4. If the input pulse frequency is reduced, these time periods become longer. On the other hand, if the frequency is increased, these time intervals become shorter. With shorter periods, more pulses occur in a given length of time and a higher average dc output voltage is produced; with longer periods, fewer pulses occur and a lower average dc output voltage is produced. Thus, the dc output is directly proportional to the repetition frequency of the input pulses. If the current and voltage are sufficiently large, a direct-reading meter can be used to indicate the count. If they are not large enough to actuate a meter directly, a dc amplifier may be added. In the latter case, a pi-type filter network is inserted at the output of R1 to absorb the instantaneous pulse variations and produce a smooth direct current for amplification.

From the preceding discussion, you should see that the voltage across the output varies in direct proportion to the input pulse repetition rate. Hence, if the repetition rate of the incoming pulses increases, the voltage across R1 also increases. For the circuit to function as a frequency counter, some method must be employed to use this frequency- to-voltage relationship to operate an indicator. The block diagram in view (A) of figure 4- 44 represents one simple circuit which may be used to perform this function. In this circuit, the basic counter is fed into a low-pass filter and an amplifier with a meter that is calibrated in units of frequency.

Figure 4-44 Basic frequency counter

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4-66 UNCLASSIFIED A typical schematic diagram is shown in view (B). The positive pulses from the counter are filtered by C2, R2, and C3. The positive dc voltage from the filter is applied to the input of amplifier A. This voltage increases with frequency; as a consequence, the current through the device increases. Since emitter or cathode current flows through M1, an increase in amplifier current causes an increase in meter deflection. The meter may be calibrated in units of time, frequency, revolutions per minute, or any function based upon the relationship of output voltage to input frequency.

Q25. What establishes the value of the current that flows in the output of figure 4-43? Q26. What is the purpose of D1 in figure 4-43? 4.9.2 Negative Counters Reversing the connections of diodes D1 and D2 in the positive-counter circuit (view (A) of figure 4-43) will cause the circuit to respond to negative pulses and become a negative-counter circuit. Diode D2 conducts during the time the negative pulse is applied and current flows in the opposite direction through R1, as was indicated by the arrow. At the end of the negative pulse, D1 conducts and discharges C1. The current through R1 increases with an increase in pulse frequency as before. However, if the voltage developed across R1 is applied to the same control circuit, as shown in view (A) of figure 4-44, the increase in current will be in a negative direction and the amplifier will conduct less. Thus, the effect is opposite to that of the positive counter.

4.9.3 Step-by-Step (Step) Counters The STEP-BY-STEP (STEP) COUNTER is used as a voltage multiplier when a stepped voltage must be provided to any device which requires such an input. The step counter provides an output which increases in one-step increments for each cycle of the input. At some predetermined level, the output voltage reaches a point which causes a circuit, such as a blocking oscillator, to be triggered.

A schematic diagram of a positive step counter is shown in view (A) of figure 4-45. For step counting, the load resistor of the positive-counting circuit is replaced by capacitor C2. This capacitor is relatively large in comparison to C1. Each time D2 conducts, the charge on C2 increases as shown in view (B). The steps are not the same height each time. They decrease exponentially with time as the voltage across C2 approaches the input voltage.

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As long as C2 has no discharge path, the voltage across its terminals increases with each successive step until it is equal in amplitude to the applied pulse. The voltage across C2 could be applied to a blocking-oscillator circuit to cause the oscillator to pulse after a certain amount of voltage is applied to it.

Figure 4-45A Basic step counter and waveforms Figure 4-45B.— Basic step counter and waveforms

NEETS MODULE 9-Wave Generation and Wave Shaping UNCLASSIFIED

4-68 UNCLASSIFIED The circuit in figure 4-46, (view A) and (view B), may be used as a frequency divider. When used in this manner, Q1 is used as a single-swing blocking oscillator that is triggered when the voltage across C2 becomes great enough to forward bias Q1. At other times, the transistor is cut off by the bias voltage developed in the section of R2 that is between the ground and the slide.

Figure 4-46A Step counter as a frequency divider and waveforms Figure 4-46B.— Step counter as a frequency divider and waveforms

NEETS MODULE 9-Wave Generation and Wave Shaping UNCLASSIFIED

4-69 UNCLASSIFIED The action of the counter can best be understood by referring back to figure 4-45. Assume C2 is 10 times larger than C1 and the peak voltage is 10 volts. C1 will assume 9/10 of the positive input voltage at T0, while C2 will assume only 1/10, or 1 volt in this example. At T1 the input will drop in a negative direction and D2 will be cut off. The cathode of D1 will become more negative than its anode and conduct, discharging C1. The charge on C2 will remain at 1 volt because it has no discharge path. At T2 the second pulse will be applied. The 1-volt charge on C2 will oppose the 10 volts of the second pulse, and the applied voltage for the capacitors to charge will be 9 volts. C2 will again charge 10 percent, or 0.9 volt. This is in addition to the initial charge of volt. At the end of the second pulse, the voltage on C2 will be 1.9 volts. At T3 the third pulse will be 10 volts, but 1.9 volts will oppose it. Therefore, the applied voltage will be 10 − 1.9 volts, or 8.1 volts. C2 will charge to 10 percent of 8.1 volts, or .81 volt. The voltage on C2 will become 1 + .9 + .81, or 2.71 volts. Successive input pulses will raise C2 by 10 percent of the remaining voltage toward 10 volts until the blocking oscillator works. If the oscillator bias is set so that Q1 begins conduction at 3.8 volts, this will continue until 3.8 volts is exceeded. Since the fourth step is 3.5 volts and the fifth is 4.1 volts, the 3.8-volt level is crossed at the fifth step. If the oscillator goes through 1 cycle of operation every fifth step and C2 is discharged at this point, this circuit would be a 5- to-1 divider.

The circuit can be made to divide by 3, 4, or some other value by setting the bias at a different level. For example, if the bias is set at 2.9 volts, conduction will occur at the fourth step, making it a 4-to-1 divider.

The counting stability of the step counter is dependent upon the exponential charging rate of capacitor C2. As C2 increases to higher steps, the voltage increments are less and less. If the ratio becomes too great, the higher steps become almost indiscernible. For this reason, accuracy decreases as the ratio increases. When you desire to count by a large number, 24 for example, a 6-to-1 counter and a 4- to-1 counter are connected in cascade (series). A more stable method of counting 24 would be to use a 2:1, 3:1, 4:1 counter connected in cascade. Most step counters operate on a ratio of 5 to 1 or less.

Q27. What is the difference between a positive counter and a step counter?

NEETS MODULE 9-Wave Generation and Wave Shaping UNCLASSIFIED

4-70 UNCLASSIFIED 4.10 SUMMARY This chapter has presented information on wave shaping. The information that follows summarizes the important points of this chapter.

A LIMITER is a device which limits or prevents some part of a waveform from exceeding a specified value.

In a SERIES LIMITER, the diode is in series with the output. It can limit either the negative or positive alternation of the input signal.

In a SERIES-POSITIVE LIMITER, the diode is in series with the output which is taken across the resistor. It removes the positive alternation of the input signal.

In a SERIES-POSITIVE LIMITER WITH BIAS, the bias potential will either aid or oppose the flow of current. When aiding forward bias, only a portion of the positive input pulse is removed. When the bias aids the reverse bias, all of the positive and a portion of the negative pulse is removed.

The SERIES-NEGATIVE LIMITER limits the negative portion of the input pulse. The difference between a series-negative limiter and a series-positive limiter is that the diode is reversed in the negative limiter.

A SERIES-NEGATIVE LIMITER with bias is the same as the series-positive limiter with bias, but the outputs are opposite. When bias aids forward bias, only a portion of the negative input is removed. When bias aids reverse bias, all of the negative and a portion of the positive input is removed.

In a PARALLEL LIMITER, a resistor and diode are connected in series with the input signal. The output is taken across the diode.

In the PARALLEL-POSITIVE LIMITER, the positive portion of the input signal is limited when the diode conducts.

The PARALLEL-NEGATIVE LIMITER diode is reversed from that of the parallel positive limiter to limit only a portion of the negative input signal.

The DUAL-DIODE LIMITER combines the parallel negative limiter with negative bias (reverse bias) and the parallel positive limiter with positive bias (reverse bias). It will remove parts of the positive and negative input signal.

NEETS MODULE 9-Wave Generation and Wave Shaping UNCLASSIFIED

4-71 UNCLASSIFIED A CLAMPING CIRCUIT effectively clamps or ties down the upper or lower extremity of a waveform to a fixed dc potential. Clamping does not change the amplitude or shape of the input waveform.

A POSITIVE CLAMPER will clamp the lower extremity of the input waveform to a dc potential of 0 volts.

A NEGATIVE CLAMPER will clamp the upper extremity of the input waveform to a dc potential of 0 volts.

A COMMON-BASE TRANSISTOR CLAMPER clamps the collector voltage to a reference level.

A waveform other than a sine wave is called a COMPLEX WAVE.

If the odd harmonics of a sine wave are added algebraically, the result is a square wave. A PERFECT SQUARE WAVE is composed of an infinite number of odd harmonics in phase with the fundamental wave.

A SAWTOOTH WAVE is made up of different harmonics, both odd and even.

A PEAKED WAVE is made up of odd harmonics that are in phase and out of phase with the fundamental.

INTEGRATION takes place in an RC circuit with the output taken across the capacitor. The amount of integration is dependent upon the time constant of the circuit. Full integration takes place when the time constant of the RC circuit is at least 10 times greater than the duration of the input pulse. An RL circuit is also used as an integration circuit. The output is taken across the resistor and the time constant of the circuit is 10 times greater than the input pulse.

DIFFERENTIATION is the opposite of integration. In the differentiator, the output is taken across the resistor. Full differentiation takes place when the time constant of the circuit is 1/10 that of the input pulse.

A COUNTING CIRCUIT receives uniform pulses, representing units to be counted, and produces a voltage output proportional to its frequency.

NEETS MODULE 9-Wave Generation and Wave Shaping UNCLASSIFIED

4-72 UNCLASSIFIED ANSWERS TO QUESTION Q1. THROUGH Q27. A1. Negative.

A2. Positive.

A3. Biasing.

A4. The diode.

A5. Conducting, cutoff.

A6. Short time constant.

A7. Long time constant.

A8. Most negative.

A9. Positive potential.

A10. Positive clamper with negative bias.

A11. Most positive.

A12. Negative potential.

A13. Positive bias.

A14. -5 volts.

A15. It is composed of an infinite number of odd harmonics in phase with the fundamental.

A16. It is composed of odd harmonics some of which are out phase with the fundamental.

A17. All the odd harmonics are in phase with the fundamental in the square wave. This is not true of the odd harmonics in the peaked wave.

A18. The time constant is long and the output is taken across the capacitor in an RC circuit.

A19. A pure sine wave cannot be integrated; it contains no harmonics.

NEETS MODULE 9-Wave Generation and Wave Shaping UNCLASSIFIED

4-73 UNCLASSIFIED A20. The ability of the inductor to oppose a change in current.

A21. The time-constant value of a long time constant-circuit is 10 times the value of the input pulse duration. The short time-constant circuit has a time constant of 1/10 of the pulse duration.

A22. A more complete integration of the waveform would result from the long time constant.

A23. In an RC circuit the output is taken across the resistor. In the RL circuit the output is taken across the inductor.

A24. Frequency counters or frequency dividers.

A25. The frequency of the voltage input.

A26. To provide a quick discharge path for C1.

A27. The load resistor in a positive counter is replaced by a capacitor in a step counter.